參數(shù)資料
型號(hào)： AT89S8253-24JC
廠商： Atmel
文件頁(yè)數(shù)： 2/60頁(yè)
文件大小： 0K
描述： IC 8051 MCU FLASH 12K 44PLCC
標(biāo)準(zhǔn)包裝： 27
系列： 89S
核心處理器： 8051
芯體尺寸： 8-位
速度： 24MHz
連通性： SPI，UART/USART
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 12KB（12K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
10
3286P–MICRO–3/10
AT89S8253
In addition, during EEPROM programming, an attempted read from the EEPROM will fetch the
byte being written with the MSB complemented. Once the write cycle is completed, true data are
valid at all bit locations.
6.1
Memory Control Register
The EECON register contains control bits for the 2K bytes of on-chip data EEPROM. It also con-
tains the control bit for the dual data pointer.
Figure 6-1.
Data EEPROM Write Sequence
Table 6-1.
EECON – Data EEPROM Control Register
EECON Address = 96H
Reset Value = XX00 0011B
Not Bit Addressable
Bit
–
EELD
EEMWE
EEMEN
DPS
RDY/BSY
WRTINH
7
654
32
1
0
Symbol
Function
EELD
EEPROM data memory load enable bit. Used to implement Page Mode Write. A MOVX instruction writing into the data
EEPROM will not initiate the programming cycle if this bit is set, rather it will just load data into the volatile data buffer of
the data EEPROM memory. Before the last MOVX, reset this bit and the data EEPROM will program all the bytes
previously loaded on the same page of the address given by the last MOVX instruction.
EEMWE
EEPROM data memory write enable bit. Set this bit to 1 before initiating byte write to on-chip EEPROM with the MOVX
instruction. User software should set this bit to 0 after EEPROM write is completed.
EEMEN
Internal EEPROM access enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM
instead of external data memory if the address used is less than 2K. When EEMEN = 0 or the address used is
≥ 2K,
MOVX with DPTR accesses external data memory.
DPS
Data pointer register select. DPS = 0 selects the first bank of data pointer register, DP0, and DPS = 1 selects the
second bank, DP1.
RDY/BSY
RDY/BSY (Ready/Busy) flag for the data EEPROM memory. This is a read-only bit which is cleared by hardware during
the programming cycle of the on-chip EEPROM. It is also set by hardware when the programming is completed. Note
that RDY/BSY will be cleared long after the completion of the MOVX instruction which has initiated the programming
cycle.
WRTINH
WRTINH (Write Inhibit) is a READ-ONLY bit which is cleared by hardware when V
cc is too low for the programming cycle
of the on-chip EEPROM to be executed. When this bit is cleared, an ongoing programming cycle will be aborted or a
new programming cycle will not start.
01
2
330
31
EEMWE
EEMEN
EELD
MOVX DATA
RDY/BSY
4 ms
~
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