參數(shù)資料
型號(hào)： AT90S1200A-4YI
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, RISC MICROCONTROLLER, PDSO20
封裝： 5.30 MM, PLASTIC, SSOP-20
文件頁(yè)數(shù)： 7/11頁(yè)
文件大?。?/td> 348K
代理商： AT90S1200A-4YI
5
AT90S1200
0838HS–AVR–03/02
Instruction Set Summary
MnemonicOperands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add Two Registers
Rd
← Rd + Rr
Z,C,N,V,H
1
ADC
Rd, Rr
Add with Carry Two Registers
Rd
← Rd + Rr +C
Z,C,N,V,H
1
SUB
Rd, Rr
Subtract Two Registers
Rd
← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd,K
Subtract Constant from Register
Rd
← Rd -K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry Two Registers
Rd
← Rd - Rr -C
Z,C,N,V,H
1
SBCI
Rd,K
Subtract with Carry Constant from Reg.Rd
← Rd -K - C
Z,C,N,V,H
1
AND
Rd, Rr
Logical AND Registers
Rd
← Rd Rr
Z,N,V
1
ANDI
Rd,K
Logical AND Register and Constant
Rd
← Rd KZ,N,V
1
ORRd, Rr
Logical ORRegisters
Rd
← Rd v Rr
Z,N,V
1
ORI
Rd,K
Logical ORRegister and Constant
Rd
← Rd v KZ,N,V
1
EORRd, Rr
Exclusive ORRegisters
Rd
← Rd
⊕ Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd
← $FF - Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd
← $00 - Rd
Z,C,N,V,H
1
SBRRd,K
Set Bit(s) in Register
Rd
← Rd v KZ,N,V
1
CBRRd,K
Clear Bit(s) in Register
Rd
← Rd (FFh -K)
Z,N,V
1
INC
Rd
Increment
Rd
← Rd +1
Z,N,V
1
DEC
Rd
Decrement
Rd
← Rd -1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd
← Rd Rd
Z,N,V
1
CLRRd
Clear Register
Rd
← Rd
⊕ Rd
Z,N,V
1
SERRd
Set Register
Rd
← $FF
None
1
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
PC
← PC + k + 1
None
2
RCALL
k
Relative Subroutine Call
PC
← PC + k + 1
None
3
RET
Subroutine Return
PC
← STACK
None
4
RETIInterrupt Return
PC
← STACK
I
4
CPSE
Rd, Rr
Compare, Skip ifEqual
if(Rd = Rr)PC
← PC + 2 or 3
None
1/2
CP
Rd, Rr
Compare
Rd - Rr
Z,N,V,C,H
1
CPC
Rd, Rr
Compare with Carry
Rd - Rr -C
Z,N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd -K
Z,N,V,C,H
1
SBRC
Rr, bSkip ifBit in Register Cleared
if(Rr(b)= 0)PC
← PC + 2 or 3
None
1/2
SBRS
Rr, bSkip ifBit in Register is Set
if(Rr(b)= 1) PC
← PC + 2 or 3
None
1/2
SBIC
P, bSkip ifBit in I/O Register Cleared
if(P(b)= 0)PC
← PC + 2 or 3
None
1/2
SBIS
P, bSkip ifBit in I/O Register is Set
if(P(b)= 1) PC
← PC + 2 or 3
None
1/2
BRBSs,k
Branch if Status Flag Set
if(SREG(s)= 1) then PC
← PC + k + 1
None
1/2
BRBC
s,k
Branch if Status FlagCleared
if(SREG(s)= 0) then PC
← PC + k + 1
None
1/2
BREQ
k
Branch ifEqual
if(Z = 1) then PC
← PC +k +1
None
1/2
BRNEk
Branch if Not Equal
if(Z = 0) then PC
← PC +k +1
None
1/2
BRCS
kBranch ifCarry Set
if(C = 1) then PC
← PC +k +1
None
1/2
BRCC
k
Branch ifCarry Cleared
if(C = 0) then PC
← PC +k +1
None
1/2
BRSH
kBranch if Same or Higher
if(C = 0) then PC
← PC +k +1
None
1/2
BRLO
k
Branch ifLower
if(C = 1) then PC
← PC +k +1
None
1/2
BRMI
k
Branch ifMinus
if(N =1) then PC
← PC +k +1
None
1/2
BRPL
k
Branch ifPlus
if(N = 0) then PC
← PC +k +1
None
1/2
BRGE
k
Branch ifGreater or Equal, Signed
if(N
⊕ V = 0) then PC ← PC +k +1
None
1/2
BRLT
kBranch ifLess than Zero, Signed
if(N
⊕ V =1) then PC ← PC +k +1
None
1/2
BRHS
kBranch if Half-carry Flag Set
if(H =1) then PC
← PC +k +1
None
1/2
BRHCk
Branch if Half-carry FlagCleared
if(H = 0) then PC
← PC +k +1
None
1/2
BRTS
kBranch if T-Flag Set
if(T =1) then PC
← PC +k +1
None
1/2
BRTCk
Branch if T-FlagCleared
if(T = 0) then PC
← PC +k +1
None
1/2
BRVS
kBranch ifOverflow Flag is Set
if(V =1) then PC
← PC + k + 1
None
1/2
BRVCk
Branch ifOverflow Flag is Cleared
if(V = 0) then PC
← PC + k + 1
None
1/2
BRIE
k
Branch ifInterrupt Enabled
if(I = 1) then PC
← PC +k +1
None
1/2
BRID
k
Branch ifInterrupt Disabled
if(I = 0) then PC
← PC +k +1
None
1/2
DATA TRANSFER INSTRUCTIONS
LD
Rd,Z
Load Register Indirect
Rd
← (Z)
None
2
ST
Z, Rr
Store Register Indirect
(Z)
← Rr
None
2
MOVRd, Rr
Move between Registers
Rd
← Rr
None
1
LDI
Rd,K
Load Immediate
Rd
← K
None
1
INRd,P
In Port
Rd
← P
None
1
OUT
P, Rr
Out Port
P
← Rr
None
1
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