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參數(shù)資料
| 型號(hào)： | AT90S1200A-4YI |
| 廠(chǎng)商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封裝： | 5.30 MM, PLASTIC, SSOP-20 |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 348K |
| 代理商： | AT90S1200A-4YI |
6
AT90S1200
0838HS–AVR–03/02
BIT AND BIT-TEST INSTRUCTIONS
SBI
P, bSet Bit in I/O Register
I/O(P,b)
← 1
None
2
CBI
P, b
Clear Bit in I/O Register
I/O(P,b)
← 0
None
2
LSL
Rd
Logical Shift LeftRd(n+1)
← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical ShiftRight
Rd(n)
← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left through Carry
Rd(0)
← C,Rd(n+1) ← Rd(n),C ← Rd(7)
Z,C,N,V
1
RORRd
Rotate Right through Carry
Rd(7)
← C,Rd(n) ← Rd(n+1),C ← Rd(0)Z,C,N,V
1
ASR
Rd
Arithmetic ShiftRight
Rd(n)
← Rd(n+1), n = 0..6Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)
← Rd(7..4),Rd(7..4) ← Rd(3..0)
None
1
BSETs
Flag Set
SREG(s)
← 1
SREG(s)1
BCLRs
FlagClear
SREG(s)
← 0SREG(s)1
BST
Rr, b
Bit Store from Register to T
T
← Rr(b)
T
1
BLD
Rd, b
Bit Load from T to Register
Rd(b)
← T
None
1
SEC
Set Carry
C
← 1C
1
CLC
Clear Carry
C
← 0
C1
SENSet Negative Flag
N
← 1
N
1
CLN
Clear Negative Flag
N
← 0N
1
SEZ
Set Zero FlagZ
← 1Z
1
CLZ
Clear Zero FlagZ
← 0
Z1
SEI
Global Interrupt Enable
I
← 1I
1
CLI
Global Interrupt Disable
I
← 0
I1
SESSet Signed Test Flag
S
← 1
S
1
CLS
Clear Signed Test Flag
S
← 0S
1
SEV
Set Two’s Complement Overflow
V
← 1
V
1
CLV
Clear Two’s Complement Overflow
V
← 0V
1
SETSet T in SREG
T
← 1
T
1
CLT
Clear T in SREG
T
← 0T
1
SEHSet Half-carry Flag in SREG
H
← 1
H
1
CLH
Clear Half-carry Flag in SREG
H
← 0H
1
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
Watchdog Reset
(see specific descr. for WDR/timer)
None
1
Instruction Set Summary(Continued)
MnemonicOperands
Description
Operation
Flags
#Clocks
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