參數(shù)資料
型號: AT90S2313-10PC
廠商: Atmel
文件頁數(shù): 27/92頁
文件大小: 0K
描述: IC MCU 2K FLSH 10MHZ UART 20DIP
標準包裝: 18
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 10MHz
連通性: SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲器容量: 2KB(1K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
33
AT90S2313
0839I–AVR–06/02
Bits 2,1,0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0
The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer/Counter1.
The Stop condition provides a Timer Enable/Disable function. The CK down divided
modes are scaled directly from the CK Oscillator clock. If the external pin modes are
used for Timer/Counter1, transitions on PD5/(T1) will clock the counter even if the pin is
configured as an output. This feature can give the user software control of the counting.
Timer/Counter1 – TCNT1H
and TCNT1L
This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To
ensure that both the high and low bytes are read and written simultaneously when the
CPU accesses these registers, the access is performed using an 8-bit temporary regis-
ter (TEMP). This temporary register is also used when accessing OCR1A and ICR1. If
the main program and interrupt routines perform access to registers using TEMP, inter-
rupts must be disabled during access from the main program or interrupts if interrupts
are re-enabled.
TCNT1 Timer/Counter1 Write:
When the CPU writes to thehighbyte TCNT1H, the writtendatais placedinthe
TEMP Register. Next, when the CPU writes the low byte TCNT1L, this byte of data
is combined with the byte data in the TEMP Register, and all 16 bits are written to
the TCNT1 Timer/Counter1 Register simultaneously. Consequently, the high byte
TCNT1H must be accessed first for a full 16-bit register write operation.
TCNT1 Timer/Counter1 Read:
When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent
to the CPU and the data of the high byte TCNT1H is placed in the TEMP Register.
When the CPU reads the data in the high byte TCNT1H, the CPU receives the data
in the TEMP Register. Consequently, the low byte TCNT1L must be accessed first
for a full 16-bit register read operation.
Table 10. Clock 1 Prescale Select
CS12
CS11
CS10
Description
0
Stop, the Timer/Counter1 is stopped.
001
CK
010
CK/8
011
CK/64
100
CK/256
1
0
1
CK/1024
1
0
External Pin T1, falling edge
1
External Pin T1, rising edge
Bit
15141312
1110
9
8
$2D ($4D)
MSB
TCNT1H
$2C ($4C)
LSB
TCNT1L
76543
210
Read/Write
R/W
Initial value
00000
000
00000
000
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