參數(shù)資料
型號： AT90S2313-10PC
廠商： Atmel
文件頁數(shù)： 76/92頁
文件大?。?/td> 0K
描述： IC MCU 2K FLSH 10MHZ UART 20DIP
標準包裝： 18
系列： AVR® 90S
核心處理器： AVR
芯體尺寸： 8-位
速度： 10MHz
連通性： SPI，UART/USART
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 15
程序存儲器容量： 2KB（1K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 20-DIP（0.300"，7.62mm）
包裝： 管件
PIC16C6X
DS30234D-page 78
1997 Microchip Technology Inc.
FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)
U-0
R/W-0
—
CCPxX
CCPxY
CCPxM3
CCPxM2
CCPxM1 CCPxM0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7
bit0
bit 7-6:
Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Signicant bits
Capture Mode
Unused
Compare Mode
Unused
PWM Mode
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000
= Capture/Compare/PWM off (resets CCPx module)
0100
= Capture mode, every falling edge
0101
= Capture mode, every rising edge
0110
= Capture mode, every 4th rising edge
0111
= Capture mode, every 16th rising edge
1000
= Compare mode, set output on match (bit CCPxIF is set)
1001
= Compare mode, clear output on match (bit CCPxIF is set)
1010
= Compare mode, generate software interrupt on match (bit CCPxIF is set, CCPx pin is unaffected)
1011
= Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1)
11xx
= PWM mode
10.1
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1 (Figure 10-2). An event is dened as:
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request ag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
10.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be cong-
ured as an input by setting the TRISC<2> bit.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Note:
If the RC2/CCP1 pin is congured as an
output, a write to PORTC can cause a cap-
ture condition.
FIGURE 10-2: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
10.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work consistently.
10.1.3
SOFTWARE INTERRUPT
When the Capture event is changed, a false capture
interrupt may be generated. The user should clear
enable bit CCP1IE (PIE1<2>) to avoid false interrupts
and should clear ag bit CCP1IF following any such
change in operating mode.
CCPR1H
CCPR1L
TMR1H
TMR1L
Set CCP1IF
PIR1<2>
Capture
Enable
Q’s
CCP1CON<3:0>
RC2/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
pin
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AT90S231310SCSL383 制造商:Atmel Corporation 功能描述:
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