參數(shù)資料
型號: AT90S8515-8AC
廠商: Atmel
文件頁數(shù): 51/112頁
文件大?。?/td> 0K
描述: IC MCU 8K FLSH 8MHZ 44TQFP
標準包裝: 160
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 內部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-TQFP
包裝: 托盤
43
AT90S8515
0841G–09/01
1.
In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must
be written to WDE even though it is set to one before the disable operation starts.
2.
Within the next four clock cycles, write a logical “0” to WDE. This disables the
Watchdog.
Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
Time-out periods are shown in Table 14.
Note:
The frequency of the Watchdog oscillator is voltage-dependent as shown in the Electrical
Characteristics section.
The WDR (Watchdog Reset) instruction should always be executed before the Watchdog
Timer is enabled. This ensures that the reset period will be in accordance with the
Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the
Watchdog Timer may not start to count from zero.
To avoid unintentional MCU reset, the Watchdog Timer should be disabled or reset
before changing the Watchdog Timer Prescale Select.
Table 14. Watchdog Timer Prescale Select
WDP2
WDP1
WDP0
Number of WDT
Oscillator Cycles
Typical Time-out
at V
CC = 3.0V
Typical Time-out
at V
CC = 5.0V
0
16K cycles
47.0 ms
15.0 ms
0
1
32K cycles
94.0 ms
30.0 ms
0
1
0
64K cycles
0.19 s
60.0 ms
0
1
128K cycles
0.38 s
0.12 s
1
0
256K cycles
0.75 s
0.24 s
1
0
1
512K cycles
1.5 s
0.49 s
1
0
1,024K cycles
3.0 s
0.97 s
1
2,048K cycles
6.0 s
1.9 s
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