參數(shù)資料
型號(hào): AT90USB647-MU
廠商: Atmel
文件頁(yè)數(shù): 78/106頁(yè)
文件大小: 0K
描述: IC AVR MCU 64K 64QFN
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 1,300
系列: AVR®
應(yīng)用: USB 微控制器
核心處理器: AVR
程序存儲(chǔ)器類型: 閃存(64 kB)
控制器系列: AT90 USB
RAM 容量: 4K x 8
接口: 2 線串行,SPI 串行,USART,USB
輸入/輸出數(shù): 48
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
供應(yīng)商設(shè)備封裝: 64-VQFN(9x9)
配用: ATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFP
ATSTK525-ND - KIT STARTER FOR AT90USB
AT90USBKEY2-ND - KIT DEMO FOR AT90USB
其它名稱: AT90USB647-16MU
AT90USB647-16MU-ND
Q4939729A
73
7593L–AVR–09/12
AT90USB64/128
11.2.2
Toggling the pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
11.2.3
Switching between input and output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) occurs. Normally, the pull-up enabled state is fully acceptable, as
a high-impedant environment will not notice the difference between a strong high driver and a
pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-
ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 11-1 summarizes the control signals for the pin value.
11.2.4
Reading the pin value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 11-2 on page 72, the PINxn Register bit and the preced-
ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure 11-3 on
page 74 shows a timing diagram of the synchronization when reading an externally applied pin
value. The maximum and minimum propagation delays are denoted t
pd, max and tpd,min
respectively.
Table 11-1.
Port pin configurations.
DDxn
PORTxn
PUD
(in MCUCR)
I/O
Pull-up
Comment
0
X
Input
No
Tri-state (Hi-Z)
0
1
0
Input
Yes
Pxn will source current if ext. pulled low
0
1
Input
No
Tri-state (Hi-Z)
1
0
X
Output
No
Output Low (Sink)
1
X
Output
No
Output High (Source)
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