參數(shù)資料
型號: AT91RM9200-EK
廠商: Atmel
文件頁數(shù): 26/41頁
文件大小: 0K
描述: DEVEL KIT
標準包裝: 1
系列: ARM®, Thumb®
類型: MCU
適用于相關產(chǎn)品: ARM920T
所含物品: 開發(fā)板,AC 適配器,線纜以及軟件
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
其它名稱: Q2427672
32
1768MS–ATARM–09-Jul-09
AT91RM9200
– Interval Measurement
– Pulse Generation
–Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
Internal interrupt signal
Two global registers that act on all three TC Channels
The Timer Counter 0 to 5 are described with five generic clock inputs, TIMER_CLOCK1 to
TIMER_CLOCK5. In the AT91RM9200, these clock inputs are connected to the Master Clock
(MCK), to the Slow Clock (SLCK) and to divisions of the Master Clock. For details, see ”Clock
Control” on page 488.
Table 10-6 gives the correspondence between the Timer Counter clock inputs and clocks in
the AT91RM9200. Each Timer Counter 0 to 5 displays the same configuration.
10.19 MultiMedia Card Interface
Compatibility with MultiMedia Card Specification Version 2.2
Compatibility with SD Memory Card Specification Version 1.0
Cards clock rate up to Master Clock divided by 2
Embedded power management to slow down clock rate when not used
Supports two slots
– One slot for one MultiMedia Card bus (up to 30 cards) or one SD Memory Card
Support for stream, block and multi-block data read and write
Connection to a Peripheral DMA Controller (PDC) channel
– Minimizes processor intervention for large buffer transfers
Table 10-6.
Timer Counter Clocks Assignment
TC Clock Input
Clock
TIMER_CLOCK1
MCK/2
TIMER_CLOCK2
MCK/8
TIMER_CLOCK3
MCK/32
TIMER_CLOCK4
MCK/128
TIMER_CLOCK5
SLCK
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