參數(shù)資料
型號: AT91RM9200-QI-002 SL383
廠商: Atmel
文件頁數(shù): 25/41頁
文件大?。?/td> 0K
描述: IC ARM MCU 16BIT 128K 208PQFP
標(biāo)準(zhǔn)包裝: 200
系列: AT91
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 180MHz
連通性: EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: POR
輸入/輸出數(shù): 122
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: ROM
RAM 容量: 48K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 208-MQFP,208-PQFP
包裝: 帶卷 (TR)
其它名稱: AT91RM9200QI002SL
31
1768MS–ATARM–09-Jul-09
AT91RM9200
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Optional hardware handshaking RTS-CTS
– Optional modem signal management DTR-DSR-DCD-RI
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
Connection of two Peripheral DMA Controller (PDC) channels
– Offers buffer transfer without processor intervention
The USART describes features allowing management of the Modem Signals DTR, DSR, DCD
and RI. For details, see ”Modem Mode” on page 435.
In the AT91RM9200, only the USART1 implements these signals, named DTR1, DSR1, DCD1
and RI1.
The USART0, USART2 and USART3 do not implement all the modem signals. Only RTS and
CTS (RTS0 and CTS0, RTS2 and CTS2, RTS3 and CTS3, respectively) are implemented in
these USARTs for other features.
Thus, programming the USART0, USART2 or the USART3 in Modem Mode may lead to unpre-
dictable results. In these USARTs, the commands relating to the Modem Mode have no effect
and the status bits relating the status of the modem signals are never activated.
10.17 Serial Synchronous Controller
Provides serial synchronous communication links used in audio and telecom applications
Contains an independent receiver and transmitter and a common clock divider
Interfaced with two PDC channels to reduce processor overhead
Offers a configurable frame sync and data length
Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
10.18 Timer Counter
Three 16-bit Timer Counter Channels
Wide range of functions including:
– Frequency Measurement
– Event Counting
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