參數(shù)資料
型號(hào): AT91RM9200-QI-002 SL383
廠商: Atmel
文件頁數(shù): 6/41頁
文件大小: 0K
描述: IC ARM MCU 16BIT 128K 208PQFP
標(biāo)準(zhǔn)包裝: 200
系列: AT91
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 180MHz
連通性: EBI/EMI,以太網(wǎng),I²C,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: POR
輸入/輸出數(shù): 122
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: ROM
RAM 容量: 48K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 208-MQFP,208-PQFP
包裝: 帶卷 (TR)
其它名稱: AT91RM9200QI002SL
14
1768MS–ATARM–09-Jul-09
AT91RM9200
6.4
PIO Controller A, B, C and D Lines
All the I/O lines PA0 to PA31, PB0 to PB29, PC0 to PC31 and PD0 to PD27 integrate a program-
mable pull-up resistor of 15 kOhm typical. Programming of this pull-up resistor is performed
independently for each I/O line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals that must be enabled as peripherals at
reset. This is explicitly indicated in the column "Reset State" of the PIO Controller multiplexing
tables.
7.
Processor and Architecture
7.1
ARM920T Processor
ARM9TDMI
-based on ARM Architecture v4T
Two instruction sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
5-Stage Pipeline Architecture:
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
16-Kbyte Data Cache, 16-Kbyte Instruction Cache
– Virtually-addressed 64-way Associative Cache
– 8 words per line
– Write-though and write-back operation
– Pseudo-random or Round-robin replacement
– Low-power CAM RAM implementation
Write Buffer
– 16-word Data Buffer
– 4-address Address Buffer
– Software Control Drain
Standard ARMv4 Memory Management Unit (MMU)
– Access permission for sections
– Access permission for large pages and small pages can be specified separately for
each quarter of the pages
– 16 embedded domains
– 64 Entry Instruction TLB and 64 Entry Data TLB
8-, 16-, 32-bit Data Bus for Instructions and Data
7.2
Debug and Test
Integrated EmbeddedICE
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