參數(shù)資料
型號(hào): AT91SAM7S32B-MU
廠商: Atmel
文件頁數(shù): 123/165頁
文件大?。?/td> 0K
描述: IC MCU ARM7 32KB FLASH 48-VQFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 250
系列: SAM7S
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 55MHz
連通性: I²C,SPI,SSC,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-VFQFN 裸露焊盤
包裝: 托盤
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
AT91SAM7S-EK-ND - KIT EVAL FOR ARM AT91SAM7S
60
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
13.3.4
Reset States
The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports
the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is per-
formed when the processor reset is released.
13.3.4.1
Power-up Reset
When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates
at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable before starting up the
device.
The startup time, as shown in Figure 13-4, is hardcoded to comply with the Slow Clock Oscillator startup time. After
the startup time, the reset signals are released and the field RSTTYP in RSTC_SR reports a Power-up Reset.
When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately.
Figure 13-4. Power-up Reset
SLCK
periph_nreset
proc_nreset
Main Supply
POR output
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 2 cycles
Startup Time
MCK
Processor Startup
= 3 cycles
Any
Freq.
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