2
參數(shù)資料
型號: AT91SAM7XC128-CU
廠商: Atmel
文件頁數(shù): 31/47頁
文件大?。?/td> 0K
描述: MCU ARM 128K HS FLASH 100-TFBGA
產(chǎn)品培訓(xùn)模塊: SAM9 MPU Boot Solutions & Application Deployment
AT91SAM7X and SAM7XC Flash-based Microcontrollers
MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 260
系列: SAM7XC
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 55MHz
連通性: CAN,以太網(wǎng),I²C,SPI,SSC,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 62
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
AT91SAM7XC-EK-ND - KIT EVAL FOR AT91SAM7XC256/128
37
6209DS–ATARM–17-Feb-09
AT91SAM7XC512/256/128
10.8
Two-wire Interface
Master Mode only
Compatibility with I
2C compatible devices (refer to the TWI section of the datasheet)
One, two or three bytes internal address registers for easy Serial Memory access
7-bit or 10-bit slave addressing
Sequential read/write operations
10.9
USART
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode
– 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB or LSB first
– Optional break generation and detection
– By 8 or by 16 over-sampling receiver frequency
– Hardware handshaking RTS - CTS
– Modem Signals Management DTR-DSR-DCD-RI on USART1
– Receiver time-out and transmitter timeguard
– Multi-drop Mode with address generation and detection
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
10.10 Serial Synchronous Controller
Provides serial synchronous communication links used in audio and telecom applications
Contains an independent receiver and transmitter and a common clock divider
Offers a configurable frame sync and data length
Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
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