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| 型號： | AT91SAM7XC256-CU-999 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 6/47頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU ARM7 256KB FLASH 100TFBGA |
| 產(chǎn)品培訓(xùn)模塊： | SAM9 MPU Boot Solutions & Application Deployment AT91SAM7X and SAM7XC Flash-based Microcontrollers MCU Product Line Introduction |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | SAM7XC |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 55MHz |
| 連通性： | CAN，以太網(wǎng)，I²C，SPI，SSC，UART/USART，USB |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 62 |
| 程序存儲(chǔ)器容量： | 256KB（256K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 64K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 1.95 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TFBGA |
| 包裝： | 帶卷 (TR) |
| 配用： | AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9 AT91SAM7XC-EK-ND - KIT EVAL FOR AT91SAM7XC256/128 |
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14
6209DS–ATARM–17-Feb-09
AT91SAM7XC512/256/128
6.
I/O Lines Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not
integrate a pull-up resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The
JTAGSEL pin integrates a permanent pull-down resistor of about 15 k
Ω.
To eliminate any risk of spuriously entering the JTAG boundary scan mode due to noise on
JTAGSEL, it should be tied externally to GND if boundary scan is not used, or pulled down with
an external low-value resistor (such as 1 k
Ω) .
6.2
Test Pin
Th e T S T p i n is used f o r ma nu f a ct ur in g t e st o r f a st pr og ra mmi ng mod e of t h e
AT91SAM7XC512/256/128 when asserted high. The TST pin integrates a permanent pull-down
resistor of about 15 k
Ω to GND.
To eliminate any risk of entering the test mode due to noise on the TST pin, it should be tied to
GND if the FFPI is not used, or pulled down with an external low-value resistor (such as 1 k
Ω) .
To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high
and PA2 tied to low.
Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.
6.3
Reset Pin
The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset
controller and can be driven low to provide a reset signal to the external components or asserted
low externally to reset the microcontroller. There is no constraint on the length of the reset pulse,
and the reset controller can guarantee a minimum pulse length. This allows connection of a sim-
ple push-button on the NRST pin as system user reset, and the use of the signal NRST to reset
all the components of the system.
The NRST pin integrates a permanent pull-up resistor to VDDIO
.
6.4
ERASE Pin
The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a
permanent pull-down resistor of about 15 k
Ω to GND.
To eliminate any risk of erasing the Flash due to noise on the ERASE pin, it shoul be tied exter-
nally to GND, which prevents erasing the Flash from the applicatiion, or pulled down with an
external low-value resistor (such as 1 k
Ω) .
This pin is debounced by the RC oscillator to improve the glitch tolerance. Minimum debouncing
time is 200 ms.
6.5
PIO Controller Lines
All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programma-
ble pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O
line through the PIO controllers.
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