參數(shù)資料
型號(hào): AT91SAM9261SB-CU
廠(chǎng)商: Atmel
文件頁(yè)數(shù): 29/39頁(yè)
文件大?。?/td> 0K
描述: IC ARM9 MPU 217-LFBGA
標(biāo)準(zhǔn)包裝: 126
系列: AT91SAM
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 190MHz
連通性: EBI/EMI,I²C,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
輸入/輸出數(shù): 96
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: ROM
RAM 容量: 48K x 8
電壓 - 電源 (Vcc/Vdd): 1.08 V ~ 1.32 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 217-LFBGA
包裝: 托盤(pán)
配用: AT91SAM9261-EK-ND - KIT EVAL FOR AT91SAM926EJ-S
AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
35
6242ES–ATARM–11-Sep-09
AT91SAM9261S
10.13 USB
USB Host Port:
– Compliance with Open HCI Rev 1.0 specification
– Compliance with USB V2.0 Full-speed and Low-speed Specification
– Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices
– Root hub integrated with two downstream USB ports
– Two embedded USB transceivers
– No overcurrent detection
– Supports power management
– Operates as a master on the Bus Matrix
USB Device Port:
– USB V2.0 full-speed compliant, 12 Mbits per second
– Embedded USB V2.0 full-speed transceiver
– Embedded dual-port RAM for endpoints
– Suspend/Resume logic
– Ping-pong mode (two memory banks) for isochronous and bulk endpoints
– Six general-purpose endpoints:
Endpoint 0: 8 bytes, no ping-pong mode
Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode
Endpoint 3: 64 bytes, no ping-pong mode
Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode
Embedded pad pull-up configurable via USB_PUCR Register located in the MATRIX user
interface
10.14 LCD Controller
Single and Dual scan color and monochrome passive STN LCD panels supported
Single scan active TFT LCD panels supported.
4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported
Up to 24-bit single scan TFT interfaces supported
Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays
1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN
1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN
1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT
Single clock domain architecture
Resolution supported up to 2048 x 2048
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