參數(shù)資料
型號: ATA6670-FFQW
廠商: Atmel
文件頁數(shù): 14/19頁
文件大?。?/td> 0K
描述: IC TXRX LIN DUAL 14VDFN
標(biāo)準(zhǔn)包裝: 6,000
系列: *
其它名稱: ATA6670-FFQW-ND
4
Atmel ATA6670 [DATASHEET]
9204F–AUTO–06/12
2.
Functional Description
The functions described in the following text apply to each LIN transceiver. Therefore, if pin LIN is stated, this applies to each of
the two receivers (LIN1 and LIN2), which work completely independently. The only internal connection is between GND1 and
GND2. The functions only available at transceiver 2 are marked accordingly.
2.1
Physical Layer Compatibility
Since the LIN physical layer is independent of higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer
according to revision 2.x can be mixed with LIN physical layer nodes, which are based on older versions (i.e., LIN 1.0, LIN 1.1,
LIN 1.2, LIN 1.3) without any restrictions.
2.2
Supply Pin (VS)
Undervoltage detection is implemented to disable transmission if VS falls to a value below 5V in order to avoid false bus
messages. After switching on VS, the corresponding transceiver switches to Fail-safe mode. The supply current for each
transceiver in Sleep mode is typically 10A.
2.3
Ground Pin (GND)
The Atmel ATA6670 does not affect the LIN bus in case of GND disconnection. It is able to handle a ground shift up to 11.5% of
VS.
2.4
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor are implemented as
specified for LIN 2.x. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN bus to VS, even
in case of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible with the LIN protocol specification. The
fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope-controlled. The output has a self-
adapting short-circuit limitation; in other words, during current limitation, the current decreases in proportion to an increase in
chip temperature.
Note:
The internal pull-up resistor is only active in normal and Fail-safe mode.
2.5
Input/Output Pin (TXD)
In Normal mode the TXD pin is the microcontroller interface to control the state of the LIN output. TXD must be at low level in
order to have a low LIN bus. If TXD is high, the LIN output transistor is turned off and the bus is in recessive state. The TXD pin
is compatible with both a 3.3V and 5V supply.
Only for the LIN transceiver 2: The TXD 2 pin is used in Fail-safe mode as an output in order to signal the wake-up source (see
<8mA.
2.6
TXD Dominant Time-out Function
The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from being driven permanently in
dominant state. If TXD is forced to low longer than tDOM > 70ms, the LIN pin is switched off (recessive mode). To reset this
mode, switch TXD to high (> 10s) before switching LIN to dominant again.
2.7
Output Pin (RXD)
This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive) is reported by a high level at RXD, LIN low
(dominant) is reported by a low voltage at RXD. The output is an open drain, therefore it is compatible with a 3.3V or 5V power
supply. The AC characteristics are defined with a pull-up resistor of 5k
Ω to 5V and a load capacitor of 20pF. The output is short
current protected. In Unpowered mode (VS = 0V) RXD is switched off. For ESD protection a Zener diode is integrated with
VZ =6.1V.
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