參數(shù)資料
型號(hào)： ATAM893T-TKSYD
廠商： Atmel
文件頁數(shù)： 3/98頁
文件大小： 0K
描述： IC MCU FLASH 4K MTP 20SSOP
標(biāo)準(zhǔn)包裝： 830
系列： MARC4
核心處理器： MARC4
芯體尺寸： 4-位
速度： 4MHz
連通性： SSI（2 線，3 線）
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲(chǔ)器容量： 4KB（4K x 8）
程序存儲(chǔ)器類型： EEPROM
EEPROM 大小： 64 x 16
RAM 容量： 256 x 4
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 6.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 20-SOIC（0.209"，5.30mm 寬）
包裝： 管件
11
4680C–4BMCU–01/05
ATAM893-D
4.2.7.3
Software Interrupts
The programmer can generate interrupts by using the Software Interrupt Instruction (SWI) which
is supported in qFORTH by predefined macros named SWI0...SWI7. The software triggered
interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the
top two elements from the expression stack and writes the corresponding bits via the I/O bus to
the interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prior-
itized or lower priority processes scheduled for later execution.
4.2.7.4
Hardware Interrupts
In the ATAM893-D, there are eleven hardware interrupt sources with seven different levels.
Each source can be masked individually by mask bits in the corresponding control registers. An
overview of the possible hardware configurations is shown in Table 4-2.
4.3
Master Reset
The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated
independent of the current program state. It can be triggered by either initial supply power-up, a
short collapse of the power supply, brown-out detection circuitry, watchdog time-out, or an exter-
nal input clock supervisor stage (see Figure 4-7 on page 12).
A master reset activation will reset the interrupt enable flag, the interrupt pending register and
the interrupt active register. During the power-on reset phase the I/O bus control signals are set
to reset mode thereby initializing all on-chip peripherals. All bi-directional ports are set to input
mode.
Attention: During any reset phase, the BP20/NTE input is driven towards V
DD by a strong pull-
up transistor. This pin must not be pulled down to V
SS during reset by any external circuitry rep-
resenting a resistor of less than 150 k
.
Releasing the reset results in a short call instruction (opcode C1h) to the EEPROM address
008h. This activates the initialization routine $RESET which in turn has to initialize all necessary
RAM variables, stack pointers and peripheral configuration registers (see Table 5-1 on page 23).
Table 4-2.
Hardware Interrupts
Interrupt
Interrupt Mask
Interrupt Source
Register
Bit
INT1
P5CR
P52M1, P52M2
P53M1, P53M2
Any edge at BP52
Any edge at BP53
INT2
T1M
T1IM
Timer 1
INT3
SISC
SIM
SSI buffer full/empty or BP40/BP43 interrupt
INT4
T2CM
T2IM
Timer 2 compare match/overflow
INT5
T3CM1
T3CM2
T3C
T3IM1
T3IM2
T3EIM
Timer 3 compare register 1 match
Timer 3 compare register 2 match
Timer 3 edge event occurs (T3I)
INT6
P5CR
P50M1, P50M2
P51M1, P51M2
Any edge at BP50
Any edge at BP51
INT7
VCM
VIM
External/internal voltage monitoring
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