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參數(shù)資料
| 型號： | ATAM893T-TKSYD |
| 廠商： | Atmel |
| 文件頁數(shù)： | 62/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 4K MTP 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 830 |
| 系列： | MARC4 |
| 核心處理器： | MARC4 |
| 芯體尺寸： | 4-位 |
| 速度： | 4MHz |
| 連通性： | SSI（2 線，3 線） |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器容量： | 4KB（4K x 8） |
| 程序存儲器類型： | EEPROM |
| EEPROM 大小： | 64 x 16 |
| RAM 容量： | 256 x 4 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 6.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 20-SOIC（0.209"，5.30mm 寬） |
| 包裝： | 管件 |
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65
4680C–4BMCU–01/05
ATAM893-D
5.3.4.5
9-bit Shift Mode
In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It always
operates as an MCL master device, i.e., SC is always generated and output by the SSI. Both the
MCL start and stop conditions are automatically generated whenever the SSI is activated or
deactivated by the SIR bit. In accordance with the MCL protocol, the output data is always
changed in the clock low phase and shifted in on the high phase.
Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate data direc-
tion for the first word must be set using the SDD control bit. The state of this bit controls the
direction of the data port (BP43 or MCL_SD). Once started, the 8 data bits are, depending on
the selected direction, either clocked into or out of the shift register. During the 9th clock period,
the port direction is automatically switched over so that the corresponding acknowledge bit can
be shifted out or read in. In transmit mode, the acknowledge bit received from the slave device is
captured in the SSI Status Register (TACK) where it can be read by the controller. In receive
mode, the state of the acknowledge bit to be returned to the slave device is predetermined by
the SSI Status Register (RACK).
Changing the directional mode (TX/RX) should not be performed during the transfer of an MCL
telegram. One should wait until the end of the telegram which can be detected using the SSI
interrupt (IFN = 1) or by interrogating the ACT status.
Once started, a 9-bit telegram will always run to completion and will not be prematurely termi-
nated by the SIR bit. So, if the SIR bit is set to ‘1’ in telegram, the SSI will complete the current
transfer and terminate the dialog with an MCL stop condition.
Figure 5-42. Example of MCL Transmit Dialog
7 6 5 432 1
7 6 5 43 210 A
msb
lsb
tx data 1
tx data 2
msb
lsb
Write STB
(tx data 1)
SC
SD
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
0A
Write STB
(tx data 2)
SIR
SDD
Start
Stop
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATAM893X-TKHYZ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Flash Version for ATAR080, ATAR090/890 and ATAR092/892 |
| ATAM893X-TKQYZ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Flash Version for ATAR080, ATAR090/890 and ATAR092/892 |
| ATAM893X-TKSYZ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Flash Version for ATAR080, ATAR090/890 and ATAR092/892 |
| ATAM894 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8k-flash Microcontroller |
| ATAM894P | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:MARC4 4-bit Microcontrollers |
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