參數(shù)資料
型號(hào)： ATF1500AL-20JU
廠商： Atmel
文件頁(yè)數(shù)： 13/19頁(yè)
文件大小： 0K
描述： IC CPLD 20NS LOW POW 44PLCC
標(biāo)準(zhǔn)包裝： 27
系列： ATF15xx
可編程類型： 系統(tǒng)內(nèi)可編程（最少 100 次編程/擦除循環(huán)）
最大延遲時(shí)間 tpd(1)： 20.0ns
電壓電源 - 內(nèi)部： 4.5 V ~ 5.5 V
宏單元數(shù)： 32
輸入/輸出數(shù)： 32
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC
包裝： 管件
ATF1500A(L)
3
Each macrocell also generates a foldback logic term, which
goes to a regional bus. All signals within a regional bus are
connected to all 16 macrocells within the region.
Cascade logic between macrocells in the ATF1500A allows
fast, efficient generation of complex logic functions. The
ATF1500A contains four such logic chains, each capable of
creating sum term logic with a fan-in of up to 40 product
terms.
Bus-friendly Pin-keeper Input and I/O’s
All Input and I/O pins on the ATF1500A have programma-
ble “pin-keeper” circuits. If activated, when any pin is driven
high or low and then subsequently left floating, it will stay at
that previous high or low level.
This circuitry prevents unused Input and I/O lines from
floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The
keeper circuits eliminate the need for external pull-up resis-
tors and eliminate their DC power consumption.
Pin-keeper circuits can be disabled. Programming is con-
trolled in the logic design file. Once the pin-keeper circuits
are disabled, normal termination procedures are required
for unused inputs and I/Os.
Speed/Power Management
The ATF1500A has several built-in speed and power man-
agement features. The ATF1500A contains circuitry that
automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only
reduces power consumption during inactive periods, but
also provides proportional power savings for most applica-
tions running at system speeds below 10 MHz.
All ATF1500As also have an optional pin-controlled power-
down mode. In this mode, current drops to below 10 mA.
When the power-down option is selected, the PD pin is
used to power-down the part. The power-down option is
selected in the design source file. When enabled, the
device goes into power-down when the PD pin is high. In
the power-down mode, all internal logic signals are latched
and held, as are any enabled outputs. All pin transitions are
ignored until the PD is brought low. When the power-down
feature is enabled, the PD cannot be used as a logic input
or output. However, the PD pin’s macrocell may still
be used to generate buried fo ldba ck and cascade
logic signals.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
Design Software Support
ATF1500A designs are supported by several third-party
tools. Automated fitters allow logic synthesis using a variety
of high-level description languages and formats.
Input Diagram
I/O Diagram
100K
V
CC
ESD
PROTECTION
CIRCUIT
INPUT
PROGRAMMABLE
OPTION
100K
V
CC
V
CC
DATA
OE
I/O
PROGRAMMABLE
OPTION
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