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參數(shù)資料
| 型號(hào)： | ATF1500AL-20JU |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 15/19頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 20NS LOW POW 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | ATF15xx |
| 可編程類(lèi)型： | 系統(tǒng)內(nèi)可編程（最少 100 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 20.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 宏單元數(shù)： | 32 |
| 輸入/輸出數(shù)： | 32 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC |
| 包裝： | 管件 |
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ATF1500A(L)
5
In addition to D, T, JK and SR operation, the flip-flop can
also be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched
when the clock is low.
The clock itself can be either the global CLK pin or an indi-
vidual product term. The flip-flop changes state on the
clock’s rising edge. When the CLK pin is used as the clock,
one of the macrocell product terms can be selected as a
clock enable. When the clock enable function is active and
the enable signal (product term) is low, all clock edges are
ignored.
The flip-flop’s asynchronous reset signal (AR) can be either
the pin global clear (GCLR), a product term, or always off.
AR can also be a logic OR of GCLR with a product term.
The asynchronous preset (AP) can be a product term or
always off.
Output Select and Enable
The ATF1500A macrocell output can be selected as regis-
tered or combinatorial. When the output is registered, the
same registered signal is fed back internally to the global
bus. When the output is combinatorial, the buried feedback
can be either the same combinatorial signal or it can be the
register output if the separate product term is chosen as
the flip-flop input.
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configu-
ration all the macrocell resources are still available, includ-
ing the buried feedback, expander and CASCADE logic.
The output enable for each macrocell can also be selected
as either of the two OE pins or as an individual product
term.
Global/Regional Busses
The global bus contains all Input and I/O pin signals as well
as the buried feedback signal from all 32 macrocells.
Together with the complement of each signal, this provides
a 68-bit bus as input to every product term. Having the
entire global bus available to each macrocell eliminates
any potential routing problems. With this architecture
designs can be modified without requiring pinout changes.
Each macrocell also generates a foldback product term.
This signal goes to the regional bus, and is available to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 16 foldback terms in each
region allow generation of high fan-in sum terms (up to 21
product terms) with little additional delay.
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