(Low Drive; C" />
參數(shù)資料
型號: ATF1502BE-7AU44
廠商: Atmel
文件頁數(shù): 8/24頁
文件大小: 0K
描述: IC CPLD EE HP 7NS 44TQFP
標準包裝: 160
系列: ATF15xx
可編程類型: 系統(tǒng)內可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 7.5ns
電壓電源 - 內部: 1.7 V ~ 1.9 V
宏單元數(shù): 32
輸入/輸出數(shù): 32
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應商設備封裝: 44-TQFP(10x10)
包裝: 托盤
配用: ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S
16
3492A–PLD–12/05
ATF1502BE
Note:
1. See ordering information for valid part numbers.
t
ZX3
Output Buffer Enable Delay
(Low Drive; CL = 35 pF)
V
CCIO = 1.8V5
6
ns
VCCIO = 3.3V
4
5
t
XZ
Output Buffer Disable Delay (C
L = 5 pF)
4
ns
tSUI
Register Setup Time
1.0
1.5
ns
tHI
Register Hold Time
0.5
ns
t
FSUI
Register Setup Time of Fast Input
0.5
1
ns
tFHI
Register Hold Time of Fast Input
0.5
ns
tRD
Register Delay
0.8
1.2
ns
t
COMB
Combinatorial Delay
0.8
1.2
ns
tIC
Array Clock Delay
2.5
3
ns
tEN
Register Enable Time
2.5
3
ns
t
GLOB
Global Control Delay
0.75
1
ns
tPRE
Register Preset Time
1.75
2
ns
tCLR
Register Clear Time
1.75
2
ns
t
UIM
Switch Matrix Delay
0.75
1
ns
t
OD3
Output Buffer and Pad Delay
(Slow slew rate = ON)
VCCIO = 1.8V2.5
3.5
ns
V
CCIO = 3.3V
1.5
2.5
ns
t
SCH
Schmitt Added Delay
1.5
2.0
ns
t
SSO
Output Buffer Pad Added Delay for
V
CCIO = 1.8V with output Low Drive
57
ns
Table 11-1.
AC Characteristics (Continued)
(1)
Symbol
Parameter
-5
-7
Units
Min
Max
Min
Max
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