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參數(shù)資料
| 型號(hào)： | ATF1502BE-7AU44 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 9/24頁 |
| 文件大小： | 0K |
| 描述： | IC CPLD EE HP 7NS 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 1.7 V ~ 1.9 V |
| 宏單元數(shù)： | 32 |
| 輸入/輸出數(shù)： | 32 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
| 配用： | ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S |
17
3492A–PLD–12/05
ATF1502BE
12. Power-down Mode
The ATF1502BE includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply cur-
rent is reduced to less than 100 A. During power-down, all output data and internal logic states
are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all
input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
ensure that pins do not float to indeterminate levels, further reducing system power. The power-
down pin feature is enabled in the logic design file or through Atmel software. Designs using the
power-down pin may not use the PD pin logic array input. However, all other PD pin macrocell
resources may still be used, including the buried feedback and foldback product term array
inputs.
Notes:
1. For low-drive outputs, add t
SSO.
2. Pin or product term.
Table 12-1.
Power-down AC Characteristics
Symbol
Parameter
-5/-7
Units
Min
Max
tIVDH
Valid I, I/O before PD High
10
ns
tGVDH
Valid OE(2) before PD High
10
ns
t
CVDH
Valid Clock(2) before PD High
10
ns
tDHIX
I, I/O Don’t Care after PD High
5
ns
tDHGX
OE(2) Don’t Care after PD High
5
ns
t
DHCX
Clock(2) Don’t Care after PD High
5
ns
tDLIV
PD Low to Valid I, I/O
2
s
t
DLGV
PD Low to Valid OE (Pin or Term)
2
s
t
DLCV
PD Low to Valid Clock (Pin or Term)
2
s
tDLOV
PD Low to Valid Output
2
s
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