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參數(shù)資料
| 型號： | ATF1504ASVL-20AU44 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 28/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 20NS LOWV LOW PWR 44TQFP |
| 標準包裝： | 160 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 20.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 64 |
| 輸入/輸出數(shù)： | 32 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-TQFP |
| 供應商設備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 608 (CN2011-ZH PDF) |
| 配用： | ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S |
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ATF1504ASV(L)
1409J–PLD–6/05
OR/XOR/CASCADE Logic
The ATF1504ASV(L)’s logic structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be routed to the OR gate, creating a
5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells,
this can be expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic
functions. One input to the XOR comes from the OR sum term. The other XOR input can
be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level
input allows polarity selection. For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used to emulate T- and JK-type
flip-flops.
Flip-flop
The ATF1504ASV(L)’s flip-flop has very flexible data and control functions. The data
input can come from either the XOR gate, from a separate product term or directly from
the I/O pin. Selecting the separate product term allows creation of a buried registered
feedback within a combinatorial output macrocell. (This feature is automatically imple-
mented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can
also be configured as a flow-through latch. In this mode, data passes through when the
clock is high and is latched when the clock is low.
The clock itself can either be one of the Global CLK Signal (GCK[0 : 2]) or an individual
product term. The flip-flop changes state on the clock’s rising edge. When the GCK sig-
nal is used as the clock, one of the macrocell product terms can be selected as a clock
enable. When the clock enable function is active and the enable signal (product term) is
low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be
either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic
OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product
term or always off.
Extra Feedback
The ATF1504ASV(L) macrocell output can be selected as registered or combinatorial.
The extra buried feedback signal can be either combinatorial or a registered signal
regardless of whether the output is combinatorial or registered. (This enhancement
function is automatically implemented by the fitter software.) Feedback of a buried com-
binatorial output allows the creation of a second latch within a macrocell.
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be
individually configured as an input, output or for bi-directional operation. The output
enable for each macrocell can be selected from the true or compliment of the two output
enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is
automatically done by the fitter software when the I/O is configured as an input, all mac-
rocell resources are still available, including the buried feedback, expander and cascade
logic.
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback sig-
nal from all 64 macrocells. The switch matrix in each logic block receives as its inputs all
signals from the global bus. Under software control, up to 40 of these signals can be
selected as inputs to the logic block.
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional
bus and is available to four macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The four foldback terms in each region allow generation of
high fan-in sum terms (up to nine product terms) with little additional delay.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1504ASVL-20JC44 | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD 64 MACROCELL w/ISP LOW PWR 3.3V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASVL-20JC68 | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD 64 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASVL-20JC84 | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD 64 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASVL-20JI44 | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD 64 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASVL-20JI68 | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD 64 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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