參數(shù)資料
型號: ATF1504ASVL-20JU44
廠商: Atmel
文件頁數(shù): 30/31頁
文件大?。?/td> 0K
描述: IC CPLD 20NS LOWV LOW PWR 44PLCC
標準包裝: 27
系列: ATF15xx
可編程類型: 系統(tǒng)內(nèi)可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 20.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
宏單元數(shù): 64
輸入/輸出數(shù): 32
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設(shè)備封裝: 44-PLCC
包裝: 管件
配用: ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S
8
ATF1504ASV(L)
1409J–PLD–6/05
Input Diagram
I/O Diagram
Speed/Power
Management
The ATF1504ASV(L) has several built-in speed and power management features. The
ATF1504ASV(L) contains circuitry that automatically puts the device into a low power
standby mode when no logic transitions are occurring. This not only reduces power con-
sumption during inactive periods, but also provides proportional power savings for most
applications running at system speeds below 5 MHz. This feature may be selected as a
device option.
To further reduce power, each ATF1504ASV(L) macrocell has a reduced-power bit fea-
ture. This feature allows individual macrocells to be configured for maximum power
savings. This feature may be selected as a design option.
All ATF1504ASV(L) also have an optional power-down mode. In this mode, current
drops to below 5 mA. When the power-down option is selected, either PD1 or PD2 pins
(or both) can be used to power down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down fea-
ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.
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