參數(shù)資料
型號: ATF1504ASVL-20JU44
廠商: Atmel
文件頁數(shù): 4/31頁
文件大?。?/td> 0K
描述: IC CPLD 20NS LOWV LOW PWR 44PLCC
標準包裝: 27
系列: ATF15xx
可編程類型: 系統(tǒng)內可編程(最少 10,000 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 20.0ns
電壓電源 - 內部: 3 V ~ 3.6 V
宏單元數(shù): 64
輸入/輸出數(shù): 32
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC
包裝: 管件
配用: ATF15XX-DK3-ND - KIT DEV FOR ATF15XX CPLD'S
12
ATF1504ASV(L)
1409J–PLD–6/05
Timing Model
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Note:
1.
Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Input
Delay
t
IN
Switch
Matrix
t
UIM
Foldback Term
Delay
t
SEXP
Register Control
Delay
t
LAC
t
IC
t
EN
Logic Array
Delay
t
LAD
Global Control
Delay
t
GLOB
Internal Output
Enable Delay
t
IOE
Cascade Logic
Delay
t
PEXP
Fast Input
Delay
t
FIN
Register
Delay
t
SU
t
H
t
PRE
t
CLR
t
RD
t
COMB
t
FSU
t
FH
Output
Delay
t
OD1
t
OD2
t
OD3
t
XZ
t
ZX1
t
ZX2
t
ZX3
I/O
Delay
t
IO
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