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參數(shù)資料
| 型號： | ATF1508ASVL-20QI160 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD EE VLOW PWR 20NS 160-PQFP |
| 標準包裝： | 24 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 20.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | ATF1508ASV20QI160 |
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1
Features
High-density, High-performance, Electrically-erasable
Complex Programmable Logic Device
– 3.0V to 3.6V Operating Range
– 128 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 84, 100, 160 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register within a COM Output
Advanced Power Management Features
– Automatic 5 A Standby for “L” Version
– Pin-controlled 100 A Standby Mode
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 84-lead PLCC and 100-lead PQFP and TQFP and
160-lead PQFP Packages
Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
Security Fuse Feature
Green (Pb/Halide-free/RoHS Compliant) Package Options
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
CC Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
High-
performance
EE PLD
ATF1508ASV
ATF1508ASVL
Rev. 1408H–PLD–7/05
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