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參數(shù)資料
| 型號： | ATF1508ASVL-20QI160 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD EE VLOW PWR 20NS 160-PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 20.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | ATF1508ASV20QI160 |
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5
ATF1508ASV(L)
1408H–PLD–7/05
Flip-flop
The ATF1508ASV(L)’s flip-flop has very flexible data and control functions. The data
input can come from either the XOR gate, from a separate product term or directly from
the I/O pin. Selecting the separate product term allows creation of a buried registered
feedback within a combinatorial output macrocell. (This feature is automatically imple-
mented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can
also be configured as a flow-through latch. In this mode, data passes through when the
clock is high and is latched when the clock is low.
The clock itself can either be the Global CLK Signal (GCK) or an individual product term.
The flip-flop changes state on the clock's rising edge. When the GCK signal is used as
the clock, one of the macrocell product terms can be selected as a clock enable. When
the clock enable function is active and the enable signal (product term) is low, all clock
edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Glo-
bal Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of
GCLEAR with a product term. The asynchronous preset (AP) can be a product term or
always off.
Figure 1. ATF1508ASV(L) Macrocell
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| ATF1508ASZ | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance E2 PLD |
| ATF1508ASZ-20AC100 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance E2 PLD |
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| ATF1508ASZ-20QC160 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance E2 PLD |
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