參數(shù)資料
型號(hào)： ATF16V8CZ-15XU
廠商： Atmel
文件頁(yè)數(shù)： 24/26頁(yè)
文件大?。?/td> 0K
描述： IC PLD 15NS 20TSSOP
標(biāo)準(zhǔn)包裝： 74
系列： 16V8
可編程類型： EE PLD
宏單元數(shù)： 8
輸入電壓： 5V
速度： 15ns
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
7
0453H–PLD–7/05
ATF16V8CZ
4.5
Power-up Reset
The ATF16V8CZ’s registers are designed to reset during power-up. At a point delayed slightly
from V
CC crossing VRST, all registers will be reset to the low state. As a result, the registered out-
put state will always be high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how V
CC actually rises in the system, the following conditions are
required:
1.
The V
CC rise must be monotonic, from below 0.7V,
2.
After reset occurs, all input and feedback setup times must be met before driving the
clock term high, and
3.
The signals from which the clock is derived must remain stable during t
PR.
4.6
Preload of Registered Outputs
The ATF16V8CZ’s registers are provided with circuitry to allow loading of each register with
either a high or a low. This feature will simplify testing since any state can be forced into the reg-
isters to control test sequencing. A JEDEC file with preload is generated when a source file with
vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automati-
cally by approved programmers.
5.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF16V8CZ fuse patterns.
Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature
remains accessible.
The security fuse should be programmed last, as its effect is immediate.
Parameter
Description
Typ
Max
Units
tPR
Power-up Reset Time
600
1,000
ns
V
RST
Power-up Reset Voltage
3.8
4.5
V
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