參數(shù)資料
型號(hào)： ATF2500C-12JL
廠商： ATMEL CORP
元件分類(lèi)： PLD
英文描述： EE PLD, 12 ns, PQCC44
封裝： PLASTIC, MS-018AC, LCC-44
文件頁(yè)數(shù)： 28/33頁(yè)
文件大?。?/td> 693K
代理商： ATF2500C-12JL
ATF2500C Family
4
T h e se cu r i ty f u se al so inh i b i t s Pr e l oa d an d Q 2
observability.
Input and I/O Pull-ups
All ATF2500C family members have programmable inter-
nal input and I/O pinkeeper circuits. When pinkeepers are
active, inputs or I/Os are not being driven externally will
maintain their last driven state. This ensures that all logic
array inputs and device outputs are known states. Pinkeep-
ers are relatively weak active circuits that can be easily
overridden by TTL-compatible drivers (see input and I/O
diagrams below).
Input Diagram
I/O Diagram
Functional Logic Diagram Description
The ATF2500C functional logic diagram describes the
interconnections between the input, feedback pins and
logic cells. All interconnections are routed through the
single global bus.
The ATF2500Cs are straightforward and uniform PLDs.
The 24 macrocells are numbered 0 through 23. Each mac-
rocell contains 17 AND gates. All AND gates have 172
inputs. The five lower product terms provide AR1, CK1,
CK2, AR2, and OE. These are: one asynchronous reset
and clock per flip-flop, and an output enable. The top 12
product terms are grouped into three sum terms, which are
used as shown in the macrocell diagrams.
Eight synchronous preset terms are distributed in a 2/4 pat-
tern. The first four macrocells share Preset 0, the next two
share Preset 1, and so on, ending with the last two macro-
cells sharing Preset 7.
The 14 dedicated inputs and their complements use the
numbered positions in the global bus as shown. Each mac-
rocell provides six inputs to the global bus: (left to right)
feedback F2
(1) true and false, flip-flop Q1 true and false,
and the pin true and false. The positions occupied by these
signals in the global bus are the six numbers in the bus dia-
gram next to each macrocell.
Note:
1. Either the flip-flop input (D/T2) or output (Q2) may be
fed back in the ATF2500Cs.
INPUT
相關(guān)PDF資料
PDF描述
ATF2500CL-20KC EE PLD, 20 ns, CQCC44
ATF2500CL-20KM EE PLD, 20 ns, CQCC44
ATF2500CL-20NM EE PLD, 20 ns, CQCC44
ATF2500CQ-25GM/883 EE PLD, 25 ns, CDIP40
ATF2500CQ-25JC EE PLD, 25 ns, PQCC44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ATF2500C-15JC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 2500 GATE 24 MACRO STD PWR 5V-15NS RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ATF2500C-15JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 2500 GATE 24 MACRO STD PWR 5V-15NS RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ATF2500C-15JN 功能描述:CPLD - 復(fù)雜可編程邏輯器件 ASICS RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ATF2500C-15JU 功能描述:CPLD - 復(fù)雜可編程邏輯器件 15 ns 24 I/O Pins 24 macorcells 48 reg RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ATF2500C-15JU SL383 制造商:Atmel Corporation 功能描述:ATF2500C 1.5K GATES 24 MC IND EEPROM 5V 44 PLCC - Tape and Reel
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