ATF2500C Family
3
Preload and Observability of
Registered Outputs
The ATF2500Cs registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A V
IH level on the odd I/O pins will force the
appropriate register high; a V
IL will force it low, independent
of the polarity or other configuration bit settings.
The PRELOAD state is entered by placing an 10.25V to
10.75V signal on SMP lead 42. When the preload clock
SMP lead 23 is pulsed high, the data on the I/O pins is
placed into the 12 registers chosen by the Q select and
even/odd select pins.
Register 2 observability mode is entered by placing an
10.25V to 10.75V signal on pin/lead 2. In this mode, the
contents of the buried register bank will appear on the
associated outputs when the OE control signals are active.
Programming Software Support
As with all other Atmel PLDs, several third party PLD devel-
opment software products and programmers will support
the ATF2500Cs.
Additionally, the ATF2500C may be programmed to per-
form the ATV2500H/Ls functional subset (no T-type flip-
flops , pin cl ock i ng or D/T 2 feedb ack ) us ing the
ATV2500H/L JEDEC file. In this case, the ATF2500C
becomes a direct replacement or speed upgrade for the
ATV2500H/L (additional GND connections are required).
Please refer to the Programmable Logic Development
Tools section for a complete PLD software and program-
mer listing.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of ATF2500C fuse patterns. Once programmed, the out-
puts will read programmed during verify.
The security fuse should be programmed last, as its effect
is immediate.
Parameter
Description
Typ
Max
Units
t
PR
Power-up Reset Time
600
1000
ns
VRST
Power-up Reset Voltage
3.8
4.5
V
Level Forced on
Odd I/O Pin during
PRELOAD Cycle
Q Select Pin
State
Even/Odd
Select
Even Q1 State
after Cycle
Even Q2 State
after Cycle
Odd Q1 State
after Cycle
Odd Q2 State
after Cycle
V
IH/VIL
Low
High/Low
X
V
IH/VIL
High
Low
X
High/Low
X
VIH/VIL
Low
High
X
High/Low
X
V
IH/VIL
High
X
High/Low