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參數(shù)資料
| 型號： | ATF750C-7SC |
| 廠商： | Atmel |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 7NS 24SOIC |
| 標(biāo)準(zhǔn)包裝： | 31 |
| 系列： | ATF750C(L) |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 宏單元數(shù)： | 10 |
| 輸入/輸出數(shù)： | 10 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 其它名稱： | ATF750C7SC |
2
0776L–PLD–11/08
ATF750C(L)
3.
Description
The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic devices.
Increased product terms, sum terms, flip-flops and output logic configurations
translate into more usable gates. High-speed logic and uniform predictable delays guarantee
fast in-system performance. The ATF750C(L) is a high-performance CMOS (electrically-eras-
able) complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-
erasable technology.
Each of the ATF750C(L)’s 22 logic pins can be used as an input. Ten of these can be used as
inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either D- or
T-type. Each flip-flop output is fed back into the array independently. This allows burying of all
the sum terms and flip-flops.
There are 171 total product terms available. There are two sum terms per output, providing
added flexibility. A variable format is used to assign between four to eight product terms per sum
term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20
sum terms and flip-flops, complex state machines are easily implemented with logic to spare.
Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop
may also be individually configured to have direct input pin controlled clocking. Each output has
its own enable product term. One product term provides a common synchronous preset for all
flip-flops. Register preload functions are provided to simplify testing. All registers automatically
reset upon power-up.
The ATF750CL is a low-power device with speeds as fast as 15 ns. The ATF750CL provides the
optimum low-power CPLD solution. This device significantly reduces total system power,
thereby allowing battery-powered operations.
2.
Pin Configurations
Pin
Function
CLK
Clock
IN
Logic Inputs
I/O
Bi-directional Buffers
GND
Ground
VCC
+5V Supply
2.1
DIP/SOIC/TSSOP
2.2
PLCC/LCC
Note:
For PLCC, pins 1, 8, 15, and 22 can be left uncon-
nected. For superior performance, connect VCC to pin 1
and GND to pins 8, 15, and 22.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
GND
VCC
I/O
IN
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IN
GND(1)
IN
I/O
GND(1)
I/O
4
3
2
1
2
8
27
26
12
13
14
15
16
17
1
8
IN
GND
(1)
IN
I/O
IN
CLK/IN
VCC
(1)
VCC
I/O
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF750C-7SX | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 750 GATE EPLD 15NS, CERDIP, 883C RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF750CL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High-speed Complex Programmable Logic Device |
| ATF750CL-15GM/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ATF750CL-15JC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 750 GATE LOW POWER - 15NS 28 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF750CL-15JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 750 GATE LOW POWER - 15NS 28 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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