參數(shù)資料
型號: ATF750C-7SC
廠商: Atmel
文件頁數(shù): 3/25頁
文件大?。?/td> 0K
描述: IC CPLD 7NS 24SOIC
標(biāo)準(zhǔn)包裝: 31
系列: ATF750C(L)
可編程類型: 系統(tǒng)內(nèi)可編程(最少 1K 次編程/擦除循環(huán))
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
宏單元數(shù): 10
輸入/輸出數(shù): 10
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 管件
其它名稱: ATF750C7SC
11
0776L–PLD–11/08
ATF750C(L)
21. Power-up Reset
The registers in the ATF750C(L)s are designed to reset during power-up. At a point delayed
slightly from V
CC crossing VRST, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how V
CC actually rises in the system, the following conditions are
required:
1.
The V
CC rise must be monotonic,
2.
After reset occurs, all input and feedback setup times must be met before driving the
clock terms or pin high, and
3.
The clock pin, or signals from which clock terms are derived, must remain stable
during t
PR.
22. Pin Capacitance
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%
tested.
Parameter
Description
Typ
Max
Units
tPR
Power-up Reset Time
600
1000
ns
V
RST
Power-up Reset Voltage
2.0
4.5
V
f = 1 MHz, T = 25°C
Typ
Max
Units
Conditions
CIN
58
pF
VIN = 0V
C
OUT
68
pF
V
OUT = 0V
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