參數(shù)資料
型號: ATMEGA1284-MUR
廠商: Atmel
文件頁數(shù): 102/160頁
文件大?。?/td> 0K
描述: IC MCU AVR 128K FLASH 44QFN
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 剪切帶 (CT)
其它名稱: ATMEGA1284-MURCT
46
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
10.11.5
Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to ”Watchdog Timer” on page 55 for details on how to configure the Watchdog Timer.
10.11.6
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
I/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 76 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to V
CC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
CC/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
10.11.7
On-chip Debug System
If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode,
the main clock source is enabled, and hence, always consumes power. In the deeper sleep
modes, this will contribute significantly to the total current consumption.
There are three alternative ways to disable the OCD system:
Disable the OCDEN Fuse
Disable the JTAGEN Fuse
Write one to the JTD bit in MCUCR
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