參數(shù)資料
型號: ATMEGA1284-MUR
廠商: Atmel
文件頁數(shù): 50/160頁
文件大?。?/td> 0K
描述: IC MCU AVR 128K FLASH 44QFN
產(chǎn)品培訓模塊: megaAVR Introduction
標準包裝: 1
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 4K x 8
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 剪切帶 (CT)
其它名稱: ATMEGA1284-MURCT
143
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
17. 8-bit Timer/Counter2 with PWM and asynchronous operation
17.1
Features
Single channel counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, phase correct Pulse Width Modulator (PWM)
Frequency generator
10-bit clock prescaler
Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
Allows clocking from external 32kHz watch crystal independent of the I/O clock
17.2
Overview
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 16-12.. For the actual
placement of I/O pins, see ”Pin configurations” on page 2. CPU accessible I/O Registers, includ-
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
The Power Reduction Timer/Counter2 bit, PRTIM2, in ”PRR0 – Power Reduction Register 0” on
page 48 must be written to zero to enable Timer/Counter2 module.
Figure 17-1. 8-bit Timer/Counter block diagram.
Timer/Counter
DA
T
A
B
U
S
OCRnA
OCRnB
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
=
Fixed
TOP
Value
Control Logic
= 0
TOP
BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TCCRnA
TCCRnB
clk
Tn
ASSRn
Synchronization Unit
Prescaler
T/C
Oscillator
clk
I/O
clk
ASY
asynchronous mode
select (ASn)
Synchronized Status flags
TOSC1
TOSC2
Status flags
clk
I/O
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