參數(shù)資料
型號： ATMEGA164A-MCHR
廠商： Atmel
文件頁數(shù)： 48/160頁
文件大?。?/td> 0K
描述： IC MCU AVR 16K 20MHZ 44QFN
產(chǎn)品培訓模塊： megaAVR Introduction
標準包裝： 1
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 8x10b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-VQFN 裸露焊盤
包裝： 剪切帶 (CT)
其它名稱： ATMEGA164A-MCHRCT
141
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the coun-
ter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
Bit 4:3 – Reserved
These bits are unused and will always read as zero.
Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOV1 Flag is set when the timer overflows. Refer to Table 16-5 on page 135 for the TOV1
Flag behavior when using another WGMn3:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
16.12.15 TIFR3 – Timer/Counter3 Interrupt Flag Register
Bit 7:6 – Reserved
These bits are unused and will always read as zero.
Bit 5 – ICF3: Timer/Counter3, Input Capture Flag
This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register
(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF3 Flag is set when the coun-
ter reaches the TOP value.
ICF3 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF3 can be cleared by writing a logic one to its bit location.
Bit
76543210
0x18 (0x38)
–
–ICF3
–
OCF3B
OCF3A
TOV3
TIFR3
Read/Write
R
R/W
R
R/W
Initial Value
00000000
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