參數(shù)資料
型號： ATMEGA164A-MUR
廠商： Atmel
文件頁數(shù)： 127/160頁
文件大?。?/td> 0K
描述： IC MCU AVR 16K 20MHZ 44VQFN
產(chǎn)品培訓模塊： MCU Product Line Introduction
megaAVR Introduction
標準包裝： 4,000
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
EEPROM 大小： 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
其它名稱： ATMEGA164A-MUR-ND
69
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are
always cleared when INT2:0 are configured as level interrupt. Note that when entering sleep
mode with the INT2:0 interrupts disabled, the input buffers on these pins will be disabled. This
may cause a logic change in internal signals which will set the INTF2:0 flags. See ”Digital Input
13.2.4
PCICR – Pin Change Interrupt Control Register
Bit 3 – PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 3 is enabled. Any change on any enabled PCINT31:24 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI3
Interrupt Vector. PCINT31:24 pins are enabled individually by the PCMSK3 Register.
Bit 2 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2
Interrupt Vector. PCINT23:16 pins are enabled individually by the PCMSK2 Register.
Bit 1 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT15:8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT15:8 pins are enabled individually by the PCMSK1 Register.
Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7:.0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt
Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register.
13.2.5
PCIFR – Pin Change Interrupt Flag Register
Bit 3– PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT31:24 pin triggers an interrupt request, PCIF3 becomes set
(one). If the I-bit in SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
Bit
7
6543
210
–
PCIE3
PCIE2
PCIE1
PCIE0
PCICR
Read/Write
RRRR
R/W
Initial Value
0
0000
000
Bit
7
6543
210
–
PCIF3
PCIF2
PCIF1
PCIF0
PCIFR
Read/Write
RRRR
R/W
Initial Value
0
0000
000
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ATMEGA164A-PU 功能描述:8位微控制器 -MCU AVR 16KB FL 512B EE 1KB SRAM-20 MHz RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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