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參數(shù)資料
| 型號(hào)： | ATMEGA164P-B15MZ |
| 廠商： | Atmel |
| 文件頁數(shù)： | 29/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 16KB FLASH 44VQFN |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 系列： | AVR® ATmega |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 16KB（8K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 44-VFQFN |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | ATMEGA164P-B15MZ-ND |
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2011 Microchip Technology Inc.
DS41391D-page 247
PIC16(L)F1826/27
25.5.2
SLAVE RECEPTION
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPxSTAT register is
cleared. The received address is loaded into the SSPx-
BUF register and acknowledged.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF of the SSPxSTAT
register is set, or bit SSPxOV of the SSPxCON1 regis-
ter is set. The BOEN bit of the SSPxCON3 register
modifies this operation. For more information see
An MSSPx interrupt is generated for each transferred
data byte. Flag bit, SSPxIF, must be cleared by soft-
ware.
When the SEN bit of the SSPxCON2 register is set,
SCLx will be held low (clock stretch) following each
received byte. The clock must be released by setting
the CKP bit of the SSPxCON1 register, except
sometimes in 10-bit mode. See Section 25.2.3 “SPI
for more detail.
25.5.2.1
7-bit Addressing Reception
This section describes a standard sequence of events
for the MSSPx module configured as an I2C Slave in
7-bit Addressing mode. All decisions made by hard-
ware or software and their effect on reception.
Figure 25-13 and Figure 25-14 is used as a visual
reference for this description.
This is a step by step process of what typically must
be done to accomplish I2C communication.
1.
Start bit detected.
2.
S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
3.
Matching address with R/W bit clear is received.
4.
The slave pulls SDAx low sending an ACK to the
master, and sets SSPxIF bit.
5.
Software clears the SSPxIF bit.
6.
Software reads received address from SSPx-
BUF clearing the BF flag.
7.
If SEN = 1; Slave software sets CKP bit to
release the SCLx line.
8.
The master clocks out a data byte.
9.
Slave drives SDAx low sending an ACK to the
master, and sets SSPxIF bit.
10. Software clears SSPxIF.
11. Software reads the received byte from SSPx-
BUF clearing BF.
12. Steps 8-12 are repeated for all received bytes
from the Master.
13. Master sends Stop condition, setting P bit of
SSPxSTAT, and the bus goes Idle.
25.5.2.2
7-bit Reception with AHEN and DHEN
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the 8th fall-
ing edge of SCLx. These additional interrupts allow the
slave software to decide whether it wants to ACK the
receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus that
was not present on previous versions of this module.
This list describes the steps that need to be taken by
slave software to use these options for I2C commun-
cation. Figure 25-15 displays a module using both
address and data holding. Figure 25-16 includes the
operation with the SEN bit of the SSPxCON2 register
set.
1.
S bit of SSPxSTAT is set; SSPxIF is set if inter-
rupt on Start detect is enabled.
2.
Matching address with R/W bit clear is clocked
in. SSPxIF is set and CKP cleared after the 8th
falling edge of SCLx.
3.
Slave clears the SSPxIF.
4.
Slave can look at the ACKTIM bit of the
SSPxCON3 register to determine if the SSPxIF
was after or before the ACK.
5.
Slave reads the address value from SSPxBUF,
clearing the BF flag.
6.
Slave sets ACK value clocked out to the master
by setting ACKDT.
7.
Slave releases the clock by setting CKP.
8.
SSPxIF is set after an ACK, not after a NACK.
9.
If SEN = 1 the slave hardware will stretch the
clock after the ACK.
10. Slave clears SSPxIF.
11. SSPxIF set and CKP cleared after 8th falling
edge of SCLx for a received data byte.
12. Slave looks at ACKTIM bit of SSPxCON3 to
determine the source of the interrupt.
13. Slave reads the received data from SSPxBUF
clearing BF.
14. Steps 7-14 are the same for each received data
byte.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
Note:
SSPxIF is still set after the 9th falling edge of
SCLx even if there is no clock stretching and
BF has been cleared. Only if NACK is sent
to Master is SSPxIF not set
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