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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ATMEGA164P-B15MZ |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋佹暩(sh霉)锛� | 42/70闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 8BIT 16KB FLASH 44VQFN |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 4,000 |
| 绯诲垪锛� | AVR® ATmega |
| 鏍稿績铏曠悊鍣細 | AVR |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 16MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 32 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 16KB锛�8K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 512 x 8 |
| RAM 瀹归噺锛� | 1K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 灏佽/澶栨锛� | 44-VFQFN |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 鍏跺畠鍚嶇ū锛� | ATMEGA164P-B15MZ-ND |
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31
7674F鈥揂VR鈥�09/09
ATmega164P/324P/644P
7.2.2
Clock Startup Sequence
Any clock source needs a sufficient V
CC to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient V
CC, the device issues an internal reset with a time-out delay (tTOUT) after
the device reset is released by all other reset sources. 鈥淥n-chip Debug System鈥� on page 45
describes the start conditions for the internal reset. The delay (t
TOUT) is timed from the Watchdog
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
selectable delays are shown in Table 7-2. The frequency of the Watchdog Oscillator is voltage
dependent as shown in Section 27. 鈥淎Tmega644P Typical Characteristics鈥� on page 338.
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The
delay will not monitor the actual voltage and it will be required to select a delay longer than the
Vcc rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be
used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay
can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is
not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-
ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal
reset active for a given number of clock cycles. The reset is then released and the device will
start to execute. The recommended oscillator start-up time is dependent on the clock type, and
varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when
the device starts up from reset. When starting up from Power-save or Power-down mode, Vcc is
assumed to be at a sufficient level and only the start-up time is included.
7.2.3
Clock Source Connections
The pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which
can be configured for use as an On-chip Oscillator, as shown in Figure 7-2 on page 32. Either a
quartz crystal or a ceramic resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. For ceramic resonators, the capacitor values given by
the manufacturer should be used.
Table 7-2.
Number of Watchdog Oscillator Cycles
Typ Time-out (V
CC = 5.0V)
Typ Time-out (V
CC = 3.0V)
Number of Cycles
0 ms
0
4.1 ms
4.3 ms
512
65 ms
69 ms
8K (8,192)
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| ATMEGA164PV-10AQR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 16KB FL 512B EE 1KB SRAM-10MHz 1.8V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| ATMEGA164PV-10AU | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 16kB Flash 0.512kB EEPROM 32 I/O Pins RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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