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| 型號： | ATMEGA16A-MUR |
| 廠商： | Atmel |
| 文件頁數(shù)： | 13/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU AVR 16KB FLASH 16MHZ 44QFN |
| 產品培訓模塊： | megaAVR Introduction |
| 標準包裝： | 4,000 |
| 系列： | AVR® ATmega |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 16KB（8K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據轉換器： | A/D 8x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-VFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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PIC16F610/616/16HV610/616
DS41288F-page 112
2009 Microchip Technology Inc.
12.3.1
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
VDD
is
required.
See
Specifications” for details. If the BOR is enabled, the
maximum rise time specification does not apply. The
BOR circuitry will keep the device in Reset until VDD
(BOR)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
12.3.2
MCLR
PIC16F610/616/16HV610/616 has a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
Voltages applied to the MCLR pin that exceed its
specification can result in both MCLR Resets and
excessive current beyond the device specification
during the ESD event. For this reason, Microchip
recommends that the MCLR pin no longer be tied
directly to VDD. The use of an RC network, as shown in
Figure 12-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RA3/MCLR pin
becomes an external Reset input. In this mode, the
RA3/MCLR pin has a weak pull-up to VDD.
FIGURE 12-2:
RECOMMENDED MCLR
CIRCUIT
12.3.3
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from an internal
RC oscillator. For more information, see Section 3.4
“Internal Clock Modes”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
VDD to rise to an acceptable level. A Configuration bit,
PWRTE, can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should be enabled when Brown-out Reset is
enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
due to:
VDD variation
Temperature variation
Process variation
See
DC
parameters
for
details
Note:
The POR circuit does not produce an
internal Reset when VDD declines. To re-
enable the POR, VDD must reach Vss for
a minimum of 100
μs.
Note:
Voltage spikes below VSS at the MCLR
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resis-
tor of 50-100 Ω should be used when
applying a “l(fā)ow” level to the MCLR pin,
rather than pulling this pin directly to VSS.
VDD
PIC MCU
MCLR
R1
1k
Ω (or greater)
C1
0.1
μF
(optional, not critical)
R2
100
Ω
(needed with capacitor)
SW1
(optional)
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