參數(shù)資料
型號(hào)： ATMEGA16A-MUR
廠商： Atmel
文件頁(yè)數(shù)： 55/88頁(yè)
文件大?。?/td> 0K
描述： MCU AVR 16KB FLASH 16MHZ 44QFN
產(chǎn)品培訓(xùn)模塊： megaAVR Introduction
標(biāo)準(zhǔn)包裝： 4,000
系列： AVR® ATmega
核心處理器： AVR
芯體尺寸： 8-位
速度： 16MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 16KB（8K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
2000 Microchip Technology Inc.
Preliminary
DS40197B-page 19
PIC16HV540
5.0
I/O PORTS
As with any other register, the I/O registers can be writ-
ten and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers (TRISA,
TRISB) are all set.
5.1
PORTA
PORTA is a 4-bit I/O register. Only the low order 4 bits
are used (RA3:RA0). Bits 7-4 are unimplemented and
read as '0's. The inputs will tolerate input voltages as
high as VIO and outputs will swing from VSS to VIO. The
internal voltage regulator VIO powers PORTA I/O pads.
The internal regulator output, VIO, is switchable
between 3Vdc and 5Vdc, via the (RL) bit in the
OPTION2 register.
5.2
PORTB
PORTB is an 8-bit I/O register (PORTB<7:0>). All 8
PORTB I/Os are high voltage I/O. The inputs will toler-
ate input voltages as high as VDD and outputs will swing
from VSS to VDD. In addition, 5 of the PORTB pins can
be configured for the wake-up on change feature. Pins
RB0, RB1, RB2 and RB3 latch the state of the pin at the
onset of sleep mode. (No “dummy” read of the PORTB
pins is required prior to executing the SLEEP instruc-
tion.) A level change on the input resets the device,
implementing wake-up on pin change. The PCWUF bit
in the status register is cleared to indicate that a pin
change caused the reset. This feature can be enabled/
disabled in the OPTION2 register.
PORTB pin RB7 also exhibits this wake-up on pin high
feature but is specially adapted for a slow-rising input
signal. This special feature prevents excessive power
consumption when desiring long sleep periods without
using the watchdog timer and prescaler. PCWUF bit in
the status register is cleared to indicate that a pin
change caused the reset. This feature can be enabled/
disabled in the OPTION2 register.
Only pins configured as inputs can cause this wake-up
on pin change to occur.
To prevent false wake-up on pin change events on pins
RB<0:3>, the pin state must be driven to a logic 1 or
logic 0 and not left floating during the “SLEEP” state.
For pin RB7, the pin state must be driven to logic 0 and
allowed to ramp to a logic 1 for correct operation.
5.3
TRIS Registers
The output driver control registers are loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the corre-
sponding output driver in a hi-impedance mode. A '0'
puts the contents of the output data latch on the
selected pins, enabling the output buffer.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
5.4
I/O Interfacing
The equivalent circuit for the PORTA and PORTB I/O
pins are shown in Figure 5-1 through Figure 5-4. All
ports may be used for both input and output operation.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF PORTB, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit (in TRISA, TRISB) must be cleared (= 0). For
use as an input, the corresponding TRIS bit must be
set. Any I/O pin can be programmed individually as
input or output.
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
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