參數(shù)資料
型號: ATMEGA324A-AUR
廠商: Atmel
文件頁數(shù): 67/160頁
文件大?。?/td> 0K
描述: IC MCU AVR 32K 20MHZ 44TQFP
產(chǎn)品培訓模塊: MCU Product Line Introduction
megaAVR Introduction
標準包裝: 2,000
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 帶卷 (TR)
其它名稱: ATMEGA324A-AUR-ND
ATMEGA324A-AURTR
159
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Note:
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at BOTTOM. See ”Fast PWM mode” on
page 149 for more details.
Table 17-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-
rect PWM mode.
Note:
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM mode” on
page 151 for more details.
Bits 3:2 – Reserved
These bits are reserved and will always read as zero.
Bits 1:0 – WGM21:0: Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 17-8. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see ”Modes of operation” on page 148).
Notes:
1. MAX= 0xFF
2. BOTTOM= 0x00
Table 17-7.
Compare Output mode, phase correct PWM mode (1).
COM2B1
COM2B0
Description
0
Normal port operation, OC2B disconnected.
01
Reserved
10
Clear OC2B on Compare Match when up-counting. Set OC2B on
Compare Match when down-counting.
11
Set OC2B on Compare Match when up-counting. Clear OC2B on
Compare Match when down-counting.
Table 17-8.
Waveform Generation mode bit description.
Mode
WGM2
WGM1
WGM0
Timer/Counter
Mode of
Operation
TOP
Update of
OCRx at
TOV Flag
Set on
0
Normal
0xFF
Immediate
MAX
10
0
1
PWM, Phase
Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
Fast PWM
0xFF
BOTTOM
MAX
4
1
0
Reserved
51
0
1
PWM, Phase
Correct
OCRA
TOP
BOTTOM
6
1
0
Reserved
7
1
Fast PWM
OCRA
BOTTOM
TOP
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