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參數(shù)資料
| 型號： | ATSAM3N1CB-CU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 30/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 64KB CORTEX-M3 100BGA |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | SAM3N |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 48MHz |
| 連通性： | I²C，IrDA，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 79 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.62 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TFBGA |
| 包裝： | 托盤 |
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36
11011BS–ATARM–22-Feb-12
SAM3N Summary
10.1
System Controller and Peripherals Mapping
Please refer to Figure 8-1, "SAM3N4/2/1/0/00 Product Mapping" on page 30.
All the peripherals are in the bit band region and are mapped in the bit band alias region.
10.2
Power-on-Reset, Brownout and Supply Monitor
The SAM3N embeds three features to monitor, warn and/or reset the chip:
Power-on-Reset on VDDIO
Brownout Detector on VDDCORE
Supply Monitor on VDDIO
10.2.1
Power-on-Reset
The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but
also during power down. If VDDIO goes below the threshold voltage, the entire chip is reset. For
more information, refer to the Electrical Characteristics section of the datasheet.
10.2.2
Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by soft-
ware through the Supply Controller (SUPC_MR). It is especially recommended to disable it
during low-power modes such as wait or sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more infor-
mation, refer to the Supply Controller (SUPC) and Electrical Characteristics sections of the
datasheet.
10.2.3
Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is inactive by default. It can be activated by software and
is fully programmable with 16 steps for the threshold (between 1.9V to 3.4V). It is controlled by
the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply monitor
power consumption by a factor of up to 2048. For more information, refer to the SUPC and Elec-
trical Characteristics sections of the datasheet.
10.3
Reset Controller
The Reset Controller is based on a Power-on-Reset cell, and a Supply Monitor on VDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either a
general reset, a wake-up reset, a software reset, a user reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin input/output. It
is capable to shape a reset signal for the external devices, simplifying to a minimum connection
of a push-button on the NRST pin to implement a manual reset.
The configuration of the Reset Controller is saved as supplied on VDDIO.
10.4
Supply Controller (SUPC)
The Supply Controller controls the power supplies of each section of the processor and the
peripherals (via Voltage regulator control)
The Supply Controller has its own reset circuitry and is clocked by the 32 kHz slow clock
generator.
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