Interrupt Handling The ATtiny26(L) has two 8-bit Interrupt Mask Control Registe" />
參數(shù)資料
型號： ATTINY26L-8PU
廠商： Atmel
文件頁數(shù)： 124/169頁
文件大?。?/td> 0K
描述： IC MCU AVR 2K 5V 8MHZ 20-DIP
產(chǎn)品培訓模塊： MCU Product Line Introduction
tinyAVR Introduction
標準包裝： 18
系列： AVR® ATtiny
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： USI
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲器容量： 2KB（1K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 11x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁面： 612 (CN2011-ZH PDF)
配用： ATSTK600-RC08-ND - STK600 ROUTING CARD AVR
ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATSTK505-ND - ADAPTER KIT FOR 14PIN AVR MCU
其它名稱： ATTINY26L-8PJ
ATTINY26L-8PJ-ND
58
1477K–AVR–08/10
ATtiny26(L)
Interrupt Handling The ATtiny26(L) has two 8-bit Interrupt Mask Control Registers; GIMSK – General Interrupt
Mask Register and TIMSK – Timer/Counter Interrupt Mask Register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are
disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set
(one) when a Return from Interrupt instruction – RETI – is executed.
When the Program Counter is vectored to the actual Interrupt Vector in order to execute the
interrupt handling routine, hardware clears the corresponding flag that generated the interrupt.
Some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to
be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the
interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by
software.
If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared (zero),
the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable
bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for as long
as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt routine. This must be handled by software.
Interrupt Response
Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. After the four clock cycles the program vector address for the actual interrupt handling
routine is executed. During this four clock cycle period, the Program Counter (10 bits) is pushed
onto the Stack. The vector is a relative jump to the interrupt routine, and this jump takes two
clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is
completed before the interrupt is served.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (10 bits) is popped back from the Stack. When AVR exits from an
interrupt, it will always return to the main program and execute one more instruction before any
pending interrupt is served. Note that the Status Register – SREG – is not handled by the AVR
hardware, neither for interrupts nor for subroutines. For the routines requiring a storage of the
SREG, this must be performed by user software.
General Interrupt
Mask Register –
GIMSK
Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
general Control Register (MCUCR) define whether the external interrupt is activated on rising or
falling edge, on pin change, or low level of the INT0 pin. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from program memory address $001. See also “External Interrupt” on
Bit
765
4321
0
$3B ($5B)
–
INT0
PCIE1
PCIE0
–
GIMSK
Read/Write
R
R/W
R
Initial Value
000
0000
0
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ATTINY26L-8SC 功能描述:8位微控制器 -MCU AVR 2K FLSH 128B EE 128B SRAM ADC 3V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
ATTINY26L-8SI 功能描述:8位微控制器 -MCU AVR 2K FLSH 128B EE 128B SRAM ADC 3V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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ATTINY26L-8SUR 功能描述:8位微控制器 -MCU 2K FL 128B EE 128B SRAM ADC 8MHZ IND 3V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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