參數(shù)資料
型號: ATTINY44A-MMHR
廠商: Atmel
文件頁數(shù): 32/135頁
文件大小: 0K
描述: MCU AVR 4KB FLASH 20MHZ 20QFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: USI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-VFQFN 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ATTINY44A-MMHRDKR
127
32015G–AVR32–09/09
AT32AP7001
Figure 14-1. INTC Block Diagram
14.4
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
14.4.1
Power Management
If the CPU enters a sleep mode that disables clocks used by the INTC, the INTC will stop func-
tioning and resume operation after the system wakes up from sleep mode.
14.4.2
Clocks
The clock for the INTC bus interface (CLK_INTC) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager.
14.4.3
Debug Operation
When an external debugger forces the CPU into debug mode, the INTC continues normal
operation.
14.5
Functional Description
All of the incoming interrupt requests (IREQs) are sampled into the corresponding Interrupt
Request Register (IRR). The IRRs must be accessed to identify which IREQ within a group that
is active. If several IREQs within the same group are active, the interrupt service routine must
prioritize between them. All of the input lines in each group are logically ORed together to form
the GrpReqN lines, indicating if there is a pending interrupt in the corresponding group.
The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to
INT3 by associating each group with the Interrupt Level (INTLEVEL) field in the corresponding
Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the
CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not
masked by the CPU status register, gets its corresponding ValReq line asserted.
Request
Masking
OR
IREQ0
IREQ1
IREQ2
IREQ31
GrpReq0
Masks
SREG
Masks
I[3-0]M
GM
INTLEVEL
AUTOVECTOR
Pr
io
ritizer
CPU
Interrupt Controller
OR
GrpReqN
NMIREQ
OR
IREQ32
IREQ33
IREQ34
IREQ63
GrpReq1
IRR Registers
IPR Registers
ICR Registers
INT_level,
offset
INT_level,
offset
INT_level,
offset
IPR0
IPR1
IPRn
IRR0
IRR1
IRRn
ValReq0
ValReq1
ValReqN
.
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