參數(shù)資料
型號: ATTINY44A-MMHR
廠商: Atmel
文件頁數(shù): 33/135頁
文件大小: 0K
描述: MCU AVR 4KB FLASH 20MHZ 20QFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
tinyAVR Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: USI
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-VFQFN 裸露焊盤
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ATTINY44A-MMHRDKR
128
32015G–AVR32–09/09
AT32AP7001
Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status
register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Inter-
rupt Mask (GM). An interrupt request is masked if either the GM or the corresponding interrupt
level mask bit is set.
The Prioritizer hardware uses the ValReq lines and the INTLEVEL field in the IPRs to select the
pending interrupt of the highest priority. If an NMI interrupt request is pending, it automatically
gets the highest priority of any pending interrupt. If several interrupt groups of the highest pend-
ing interrupt level have pending interrupts, the interrupt group with the highest number is
selected.
The INTLEVEL and handler autovector offset (AUTOVECTOR) of the selected interrupt are
transmitted to the CPU for interrupt handling and context switching. The CPU does not need to
know which interrupt is requesting handling, but only the level and the offset of the handler
address. The IRR registers contain the interrupt request lines of the groups and can be read via
user interface registers for checking which interrupts of the group are actually active.
14.5.1
Non-Maskable Interrupts
A NMI request has priority over all other interrupt requests. NMI has a dedicated exception vec-
tor address defined by the AVR32 architecture, so AUTOVECTOR is undefined when
INTLEVEL indicates that an NMI is pending.
14.5.2
CPU Response
When the CPU receives an interrupt request it checks if any other exceptions are pending. If no
exceptions of higher priority are pending, interrupt handling is initiated. When initiating interrupt
handling, the corresponding interrupt mask bit is set automatically for this and lower levels in sta-
tus register. E.g, if an interrupt of level 3 is approved for handling, the interrupt mask bits I3M,
I2M, I1M, and I0M are set in status register. If an interrupt of level 1 is approved, the masking
bits I1M and I0M are set in status register. The handler address is calculated by adding
AUTOVECTOR to the CPU system register Exception Vector Base Address (EVBA). The CPU
will then jump to the calculated address and start executing the interrupt handler.
Setting the interrupt mask bits prevents the interrupts from the same and lower levels to be
passed through the interrupt controller. Setting of the same level mask bit prevents also multiple
requests of the same interrupt to happen.
It is the responsibility of the handler software to clear the interrupt request that caused the inter-
rupt before returning from the interrupt handler. If the conditions that caused the interrupt are not
cleared, the interrupt request remains active.
14.5.3
Clearing an Interrupt Request
Clearing of the interrupt request is done by writing to registers in the corresponding peripheral
module, which then clears the corresponding NMIREQ/IREQ signal.
The recommended way of clearing an interrupt request is a store operation to the controlling
peripheral register, followed by a dummy load operation from the same register. This causes a
pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is
exited and the interrupt mask is cleared before the interrupt request is cleared.
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