參數(shù)資料
型號(hào)： AV80C51T-12R
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44
文件頁數(shù)： 58/170頁
文件大小： 4133K
代理商： AV80C51T-12R
150
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
19. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add without Carry
Rd
Rd + Rr
Z,C,N,V,S,H
1
ADC
Rd, Rr
Add with Carry
Rd
Rd + Rr + C
Z,C,N,V,S,H
1
SUB
Rd, Rr
Subtract without Carry
Rd
Rd - Rr
Z,C,N,V,S,H
1
SUBI
Rd, K
Subtract Immediate
Rd
Rd - K
Z,C,N,V,S,H
1
SBC
Rd, Rr
Subtract with Carry
Rd
Rd - Rr - C
Z,C,N,V,S,H
1
SBCI
Rd, K
Subtract Immediate with Carry
Rd
Rd - K - C
Z,C,N,V,S,H
1
AND
Rd, Rr
Logical AND
Rd
Rd Rr
Z,N,V,S
1
ANDI
Rd, K
Logical AND with Immediate
Rd
Rd K
Z,N,V,S
1
OR
Rd, Rr
Logical OR
Rd
Rd v Rr
Z,N,V,S
1
ORI
Rd, K
Logical OR with Immediate
Rd
Rd v K
Z,N,V,S
1
EOR
Rd, Rr
Exclusive OR
Rd
Rd Rr
Z,N,V,S
1
COM
Rd
One’s Complement
Rd
$FF Rd
Z,C,N,V,S
1
NEG
Rd
Two’s Complement
Rd
$00 Rd
Z,C,N,V,S,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd
Rd v K
Z,N,V,S
1
CBR
Rd,K
Clear Bit(s) in Register
Rd
Rd ($FFh - K)
Z,N,V,S
1
INC
Rd
Increment
Rd
Rd + 1
Z,N,V,S
1
DEC
Rd
Decrement
Rd
Rd 1
Z,N,V,S
1
TST
Rd
Test for Zero or Minus
Rd
Rd Rd
Z,N,V,S
1
CLR
Rd
Clear Register
Rd
Rd Rd
Z,N,V,S
1
SER
Rd
Set Register
Rd
$FF
None
1
BRANCH INSTRUCTIONS
RJMP
k
Relative Jump
PC
PC + k + 1
None
2
IJMP
Indirect Jump to (Z)
PC(15:0)
Z, PC(21:16) 0None
2
RCALL
k
Relative Subroutine Call
PC
PC + k + 1
None
3/4
ICALL
Indirect Call to (Z)
PC(15:0)
Z, PC(21:16) 0None
3/4
RET
Subroutine Return
PC
STACK
None
4/5
RETI
Interrupt Return
PC
STACK
I
4/5
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC
PC + 2 or 3
None
1/2/3
CP
Rd,Rr
Compare
Rd
Rr
Z, C,N,V,S,H
1
CPC
Rd,Rr
Compare with Carry
Rd
Rr C
Z, C,N,V,S,H
1
CPI
Rd,K
Compare with Immediate
Rd
Z, C,N,V,S,H
1
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC
PC + 2 or 3
None
1/2/3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC
PC + 2 or 3
None
1/2/3
SBIC
A, b
Skip if Bit in I/O Register Cleared
if (I/O(A,b)=0) PC
PC + 2 or 3
None
1/2/3
SBIS
A, b
Skip if Bit in I/O Register is Set
if (I/O(A,b)=1) PC
PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC
PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC
PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC
PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC
PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC
PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC
PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC
PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC
PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC
PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC
PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N
V= 0) then PC PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N
V= 1) then PC PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC
PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC
PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC
PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC
PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC
PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC
PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC
PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC
PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
LSL
Rd
Logical Shift Left
Rd(n+1)
Rd(n), Rd(0) 0
Z,C,N,V,H
1
LSR
Rd
Logical Shift Right
Rd(n)
Rd(n+1), Rd(7) 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)
C,Rd(n+1) Rd(n),CRd(7)
Z,C,N,V,H
1
ROR
Rd
Rotate Right Through Carry
Rd(7)
C,Rd(n) Rd(n+1),CRd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n)
Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)
Rd(7..4),Rd(7..4)Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s)
1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s)
0
SREG(s)
1
SBI
A, b
Set Bit in I/O Register
I/O(A, b)
1None
1
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