- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295115 > AX1000-1FG676I FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA676 PDF資料下載
參數(shù)資料
| 型號： | AX1000-1FG676I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA676 |
| 封裝： | 1 MM PITCH, FBGA-676 |
| 文件頁數(shù)： | 7/230頁 |
| 文件大小： | 6485K |
| 代理商： | AX1000-1FG676I |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁
Axcelerator Family FPGAs
2- 90
v2.8
Instruction Register (IR) and the Data Registers (such as
BSR,
IDCODE,
USRCODE,
BYPASS,
etc.).
The
TAP
Controller steps into one of the states depending on the
sequence of TMS at the rising edges of TCK.
Instruction Register (IR)
The IR has five bits (IR4 to IR0). At the TRST state, IR is
reset to IDCODE. Each time when IR is selected, it goes
through "select IR-Scan," "Capture-IR," "Shift-IR," all the
way through "Update-IR." When there is no test error,
the first five data bits coming out of TDO during the
"Shift-IR" will be "10111." If a test error occurs, the last
three bits will contain one to three zeroes corresponding
to
negatively
asserted
signals:
"TDO_ERRORB,"
"PROBA_ERRORB," and "PROBB_ERRORB." The error(s)
will be erased when the TAP is at the "Update-IR" or the
TRST state. When in user mode start-up sequence, if the
micro-probe has not been used, the "PROBA_ERRORB" is
used as a "Power-up done successfully" flag.
Data Registers (DRs)
Data registers are distributed throughout the chip. They
store testing/programming vectors. The MSB of a data
register is connected to TDI, while the LSB is connected
to TDO. There are different types of data registers.
Descriptions of the main registers are as follow:
1. IDCODE:
The IDCODE is a 33-bit hard coded JTAG Silicon
Signature. It is a hardwired device ID code, which
contains the Actel identity, part number, and version
number in a specific JTAG format.
2. USERCODE:
The USERCODE is a 32-bit programmable JTAG Silicon
Signature. It is a supplementary identity code for the
user to program information to distinguish different
programmed parts. USERCODE fuses will read out as
"zeroes" when not programmed, so only the "1" bits
need to be programmed.
3. Boundary-Scan Register (BSR):
Each I/O contains three Boundary-Scan Cells. Each cell
has a shift register bit, a latch, and two MUXes. The
boundary-scan cells are used for the Output-enable
(E), Output (O), and Input (I) registers. The bit order
of the boundary-scan cells for each of them is E-O-I.
The boundary-scan cells are then chained serially to
form the Boundary-Scan Register (BSR). The length of
the BSR is the number of I/Os in the die multiplied by
three.
4. Bypass Register (BYR):
This is the "1-bit" register. It is used to shorten the
TDI-TDO serial chain in board-level testing to only
one bit per device not being tested. It is also selected
for all "reserved" or unused instructions.
Probing
Internal activities of the JTAG interface can be observed
via the Silicon Explorer II probes: "PRA," "PRB," "PRC,"
and "PRD."
Special Fuses
Security
Actel antifuse FPGAs, with FuseLock technology, offer
the highest level of design security available in a
programmable logic device. Since antifuse FPGAs are
live-at power-up, there is no bitstream that can be
intercepted, and no bitstream or programming data is
ever downloaded to the device during power-up, thus
making device cloning impossible.
In addition, special
security fuses are hidden throughout the fabric of the
device and may be programmed by the user to thwart
attempts to reverse engineer the device by attempting
to exploit either the programming or probing interfaces.
Both invasive and noninvasive attacks against an
Axcelerator device that access or bypass these security
fuses will destroy access to the rest of the device. (refer
FPGAs white paper).
Look for this symbol to ensure your valuable IP is secure.
To ensure maximum security in Axcelerator devices, it is
recommended that the user program the device security
fuse (SFUS). When programmed, the Silicon Explorer II
testing probes are disabled to prevent internal probing,
and the programming interface is also disabled. All JTAG
public instructions are still accessible by the user.
For more information, refer to Actel’s Implementation of
Security in Actel Antifuse FPGAs application note.
Global Set Fuse
The Global Set Fuse determines if all R-cells and I/O
registers (InReg, OutReg, and EnReg) are either cleared
or preset by driving the GCLR and GPSET inputs of all R-
cells and I/O Registers (Figure 2-31 on page 2-47). Default
setting is to clear all registers (GCLR = 0 and GPSET =1) at
device power-up. When the GBSETFUS option is checked
during FUSE file generation, all registers are preset
(GCLR = 1 and GPSET= 0). A local CLR or PRESET will take
precedence over this setting. Both pins are pulled High
during normal device operation. For use details, see the
Libero IDE online help.
Figure 2-69 FuseLock Logo
e
u
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX1000-1FG676MX79 | FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA676 |
| AX1000-1FG676M | FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA676 |
| AX1000-1FG676X79 | FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA676 |
| AX1000-1FG676 | FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA676 |
| AX1000-1FG896IX79 | FPGA, 12096 CLBS, 612000 GATES, 763 MHz, PBGA896 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX1000-1FG676M | 制造商:Microsemi Corporation 功能描述:FPGA Axcelerator Family 612K Gates 12096 Cells 763MHz 0.15um Technology 1.5V 676-Pin FBGA 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 612K GATES 12096 CELLS 763MHZ 0.15UM 1.5V 6 - Trays |
| AX1000-1FG896 | 功能描述:IC FPGA AXCELERATOR 1M 896-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| AX1000-1FG896B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX1000-1FG896I | 功能描述:IC FPGA AXCELERATOR 1M 896-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Axcelerator 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| AX1000-1FG896M | 制造商:Microsemi Corporation 功能描述:FPGA Axcelerator Family 612K Gates 12096 Cells 763MHz 0.15um Technology 1.5V 896-Pin FBGA 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 612K GATES 12096 CELLS 763MHZ 0.15UM 1.5V 8 - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。