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參數(shù)資料
| 型號： | AX250-CQ352M |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, CQFP352 |
| 封裝： | 0.50 MM PITCH, CERAMIC, QFP-352 |
| 文件頁數(shù)： | 6/230頁 |
| 文件大小： | 6485K |
| 代理商： | AX250-CQ352M |
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Axcelerator Family FPGAs
v2.8
2-89
Building RAM and FIFO Modules
RAM and FIFO modules can be generated and included
in a design in two different ways:
Using the SmartGen Core Generator where the
user defines the depth and width of the FIFO/
RAM, and then instantiates this block into the
design
(please
refer
to
Actel’s
Memory System Builder User’s Guide for more
information).
The alternative is to instantiate the RAM/FIFO
blocks manually, using inverters for polarity
control and tying all unused data bits to ground.
Other Architectural Features
Low Power Mode
Although designed for high performance, the AX
architecture also allows the user to place the device into
a low power mode. Each I/O bank in an Axcelerator
device can be configured individually, when in low
power mode, to tristate all outputs, disable inputs, or
both. The low power mode is activated by asserting the
LP pin, which is grounded in normal operation.
While in the low power mode, the device is still fully
functional and all internal logic states are preserved. This
allows a user to disable all but a few signals and operate
the part in a low-frequency, watchdog mode if desired.
Please note, if the I/O bank is not disabled, differential I/Os
belonging to the I/O bank will still consume normal
power, even when operating in the low power mode.
The Axcelerator device will resume normal operation
10
μs after the LP pin is pulled Low.
To further reduce power consumption, the internal
charge pump can be bypassed and an external power
supply voltage can be used instead. This saves the
internal charge-pump operating current, resulting in no
DC current draw. The Axcelerator family devices have a
dedicated "VPUMP" pin that can be used to access an
external charge pump device. In normal chip operation,
when using the internal charge pump, VPUMP should be
tied to GND. When the voltage level on VPUMP is set to
3.3V, the internal charge pump is turned off, and the
VPUMP voltage will be used as the charge pump voltage.
Adequate voltage regulation (i.e. high drive, low output
impedance, and good decoupling) should be used at
VPUMP.
In addition, any PLL in use can be powered down to
further reduce power consumption. This can be done
with the PowerDown pin driven Low. Driving this pin
High restarts the PLL with the output clock(s) being
stable once lock is restored.
JTAG
Axcelerator offers a JTAG interface that is compliant with
the IEEE 1149.1 standard. The user can employ the JTAG
interface for probing a design and performing any JTAG
Public Instructions as defined in the Table 2-102.
Interface
The interface consists of four inputs: Test Mode Select
(TMS), Test Data In (TDI), Test Clock (TCK), TAP Controller
Reset (TRST), and an output, Test Data Out (TDO). TMS,
TDI, and TRST have on-chip pull-up resistors.
TRST
TRST (Test-Logic Reset) is an active-low, asynchronous
reset signal to the TAP controller. The TRST input can be
used to reset the Test Access Port (TAP) Controller to the
TRST state. The TAP Controller can be held at this state
permanently by grounding the TRST pin. To hold the
JTAG TAP controller in the TRST state, it is recommended
to connect TRST to ground via a 1 k
Ω resistor.
There is an optional internal pull-up resistor available for
the TRST input that can be set by the user at
programming. Care should be exercised when using this
option in combination with an external tie-off to
ground.
An on-chip power-on-reset (POWRST) circuit is included.
POWRST has the same function as "TRST," but it only
occurs at power-up or during recovery from a VCCA and/
or VCCDA voltage drop.
TDO
TDO is normally tristated, and it is active only when the
TAP controller is in the "Shift_DR" state or "Shift_IR"
state. The least significant bit of the selected register (i.e.
IR or DR) is clocked out to TDO first by the falling edge of
TCK.
TAP Controller
The TAP Controller is compliant with the IEEE Standard
1149.1. It is a state machine of 16 states that controls the
Table 2-102 JTAG Instruction Code
Instruction (IR4:IR0)
Binary Code
Extest
00000
Preload / Sample
00001
Intest
00010
USERCODE
00011
IDCODE
00100
HIGHZ
01110
CLAMP
01111
Diagnostic
10000
Reserved
All others
Bypass
11111
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| AX250-FG484M | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA484 |
| AX250-PQ208M | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PQFP208 |
| AX250-1FGG256 | FPGA, 2816 CLBS, 154000 GATES, 763 MHz, PBGA256 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AX250-CQ896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-CQ896B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-CQ896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-CQ896M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-CQ896PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
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