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參數(shù)資料
| 型號(hào)： | AX250-FG256M |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA256 |
| 封裝： | 1 MM PITCH, FBGA-256 |
| 文件頁(yè)數(shù)： | 8/230頁(yè) |
| 文件大?。?/td> | 6485K |
| 代理商： | AX250-FG256M |
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Axcelerator Family FPGAs
v2.8
2-91
Silicon Explorer II Probe Interface
Silicon Explorer II is an integrated hardware and
software solution that, in conjunction with the Designer
tools, allows users to examine any of the internal nets
(except I/O registers) of the device while it is operating in
a prototype or a production system. The user can probe
up to four nodes at a time without changing the
placement and routing of the design and without using
any additional device resources. Highlighted nets in
Designer’s ChipPlanner can be accessed using Silicon
Explorer II in order to observe their real time values.
Silicon Explorer II's noninvasive method does not alter
timing or loading effects, thus shortening the debug
cycle. In addition, Silicon Explorer II does not require
relayout or additional MUXes to bring signals out to
external
pins,
which
is
necessary
when
using
programmable logic devices from other suppliers. By
eliminating multiple place-and-route program cycles, the
integrity of the design is maintained throughout the
debug process.
Each member of the Axcelerator family has four external
pads: PRA, PRB, PRC, and PRD. These can be used to bring
out four probe signals from the Axcelerator device (note
that the AX125 only has two probe signals that can be
observed: PRA and PRB). Each core tile has up to two
probe signals. To disallow probing, the SFUS security fuse
in the silicon signature has to be programmed (see
Silicon Explorer II connects to the host PC using a
standard serial port connector. Connections to the circuit
board are achieved using a nine-pin D-Sub connector
(Figure 1-9 on page 1-7). Once the design has been
placed-and-routed, and the Axcelerator device has been
programmed, Silicon Explorer II can be connected and
the Explorer software can be launched.
Silicon Explorer II comes with an additional optional PC
hosted tool that emulates an 18-channel logic analyzer.
Four channels are used to monitor four internal nodes,
and 14 channels are available to probe external signals.
The software included with the tool provides the user
with an intuitive interface that allows for easy viewing
and editing of signal waveforms.
Programming
Device programming is supported through the Silicon
Sculptor II, a single-site, robust and compact device
programmer for the PC. Up to four Silicon Sculptor IIs can
be daisy-chained and controlled from a single PC host.
With standalone software for the PC, Silicon Sculptor II is
designed to allow concurrent programming of multiple
units from the same PC when daisy-chained.
Silicon Sculptor II programs devices independently to
achieve the fastest programming times possible. Each
fuse is verified by Silicon Sculptor II to ensure correct
programming. Furthermore, at the end of programming,
there are integrity tests that are run to ensure that
programming was completed properly. Not only does it
test programmed and nonprogrammed fuses, Silicon
Sculptor II also provides a self-test to test its own
hardware extensively.
Programming
an
Axcelerator
device
using
Silicon
Sculptor II is similar to programming any other antifuse
device. The procedure is as follows:
1. Load the .AFM file.
2. Select the device to be programmed.
3. Begin programming.
When the design is ready to go to production, Actel
offers
device
volume-programming
services
either
through distribution partners or via our In-House
Programming Center.
In
addition,
BP
Microsystems
offers
multi-site
programmers
that
provide
qualified
support
for
Axcelerator devices.
For more details on programming the Axcelerator
devices, please refer to the Silicon Sculptor II User’s
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX250-FG256X79 | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA256 |
| AX250-FG256 | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA256 |
| AX250-FG484IX79 | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA484 |
| AX250-FG484I | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA484 |
| AX250-FG484MX79 | FPGA, 2816 CLBS, 154000 GATES, 649 MHz, PBGA484 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX250-FG484 | 功能描述:IC FPGA AXCELERATOR 250K 484FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Axcelerator 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| AX250-FG484I | 功能描述:IC FPGA AXCELERATOR 250K 484FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Axcelerator 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| AX250-FG484M | 制造商:Microsemi Corporation 功能描述:FPGA AXCELERATOR 154K GATES 2816 CELLS 649MHZ 0.15UM 1.5V 48 - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 248 I/O 484FBGA |
| AX250-FG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
| AX250-FG896B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Axcelerator Family FPGAs |
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