參數(shù)資料
型號(hào): AX88178L
廠商: Electronic Theatre Controls, Inc.
英文描述: USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller
中文描述: USB接口10/100/1000千兆以太網(wǎng)/電話線網(wǎng)絡(luò)控制器
文件頁(yè)數(shù): 24/35頁(yè)
文件大?。?/td> 218K
代理商: AX88178L
ASIX ELECTRONICS CORPORATION
24
AX88178 L
USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller
6.2.2 Remote Wakeup Description
After AX88178 enters into suspend mode, either the USB host or AX88178 itself can awake it up and resume back to the
original operation mode before it entered suspend. Following truth table shows the chip setting, wakeup event, and device
response supported by this ASIC. Note that “X” stands for don’t-care.
Setting
Wakeup
by
RWU bit
of Flag
byte in
EEPRO
M
Host
X
X
X
X
J -> K
Device
0
0
X
X
Device
1
1
0
1
Device
1
1
1
0
Device
1
1
1
0
Device
1
1
X
X
Wakeup Event
Device
awakes up
Set_Feature
standard
command
RWLU of
Monitor
Mode
Register
RWMP of
Monitor
Mode
register
Host send
resume
signal
Receiving
Magic
Packet
EXTWAKE
UP_N pin
Linkup
detected
on
Primary
Phy
X
Yes
Linkup
detected on
Secondary
Phy
Yes
No
Yes
Yes
Yes
Yes
X
Yes
X
X
Yes
Low-pulse
Table 5: Remote Wakeup Truth Table
6.3 Interrupt Endpoint
The Interrupt Endpoint contains 8 bytes of data and its frame format is defined as: A100_BB00_CCDD_EEFF.
Where BB byte in byte 3:
Bit7
Bit6
Bit5
Bit4
Bit3
Reserved
MDINT
PPLS: Primarily PHY Link State.
1: Link is up.
0: Link is down.
SPLS: Secondary PHY Link State.
1: Link is up.
0: Link is down.
FLE: Bulk Out Ethernet Frame Length Error.
1: Proprietary Length field has parity error during Bulk Out transaction.
0: Proprietary Length field has no parity error during Bulk Out transaction.
MDINT: Input level of MDINT pin. The MDINT pin can be connectted to MDINT# pin of Ethernet Phy.
1: When MDINT input pin = 1.
0: When MDINT input pin = 0.
CCDD byte in byte 5 and 6: Primary Phy’s register value, whose offset is given in High byte of EEPROM offset 0Fh.
EEFF byte in byte 7 and 8: Primary Phy’s register value, whose offset is given in Low byte of EEPROM offset 0Fh.
Bit2
FLE
Bit1
SPLS
Bit0
PPLS
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