
B9948
Document #: 38-07079 Rev. *B
Page 4 of 6
Notes:
5.
6.
7.
8.
9.
10. Set-up and Hold times are relative to the falling edge of the input clock
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
Outputs driving 50
transmission lines.
50% input duty cycle.
Outputs loaded with 30 pF each
Note:The ordering part number is formed by a combination of device number, device revision, package style, and screening as
shown below.
AC Parameters
[5]
:
V
DDC
= 3.3V ±10%, V
DD
= 3.3V ±10%, T
A
=
–
40
°
C to +85
°
C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Maximum Input Frequency
[6]
PECL_CLK to Q Delay
[6]
TCLK to Q Delay
[6]
Output Duty Cycle
[6,7]
160
MHz
Tpd
4.0
8.0
ns
4.4
8.9
FoutDC
Measured at V
DDC
/2
TCYCLE/2
–
800
TCYCLE/2 + 800
ps
tpZL, tpZH
Output enable time (all outputs)
2
10
ns
tpLZ, tpHZ
Output disable time (all outputs)
Output-to-Output Skew
[6,8]
Part-to-Part Skew
[9]
2
10
ns
Tskew
350
ps
Tskew (pp)
PECL_CLK to Q
1.5
ns
TCLK to Q
2.0
Ts
Set-up Time
[6,10]
SYNC_OE to PECL_CLK
1.0
ns
SYNC_OE to TCLK
0.0
Th
Hold Time
[6,10]
PECL_CLK to SYNC_OE
0.0
ns
TCLK to SYNC_OE
1.0
Tr/Tf
Output Clocks Rise/Fall Time
[8]
0.8V to 2.0V
0.2
1.0
ns
Ordering Information
Part Number
B9948CA
Package Type
32-Pin TQFP
Production Flow
Industrial,
–
40
°
C to +85
°
C
Marking: Example:
Cypress
B9948CA
Date Code, Lot #
B9948CA
Package
A = TQFP
Revision
Device Number